Intel Corporation

Other

Mani Ayyar

Akhilesh Kumar

Ioannis T Schoinas

Suresh K Marisetty

Jose Andy Vargas

Eric R Delano

Andrew J Fish

Sham M Datta

Doddaballapur N Jayasimha

George Thangadurai

Jay Jayasimha

Murugasamy K Nachimuthu

Srinivas Chennupaty

Nhon Toai Quach

Phanindra Mannava

Yan Li

Bernard Lint

Mohan J Kumar

Stephen S Pawlowski

Gary N Hammond

Shivnandan D Kaushik

Douglas Raymond Moran

Eshwari Prasad Komarla

Rama R Menon

Amy L O'Donnell

Aniruddha Vaidya

Ioannis Yannis Schoinas

Russ Wunderlich

Doddabaliapur Narasimha-Murthy Jayasimha

A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.

Method, system, and apparatus for dynamic reconfiguration of resources

Multiple initialization techniques for system and component in a point-to-point architecture are discussed. Consequently, the techniques allow for flexible system/socket layer parameters to be tailored to the needs of the platform, such as, desktop, mobile, small server, large server, etc., as well as the component types such as IA32/IPF processors, memory controllers, IO Hubs, etc. Furthermore, the techniques facilitate powering up with the correct set of POC values, hence, it avoids multiple warm resets and improves boot time. In one embodiment, registers to hold new values, such as, Configuration Values Driven during Reset (CVDR), and Configuration Values Captured during Reset (CVCR) may be eliminated. For example, the POC values could be from the following: Platform Input Clock to Core Clock Ratio, Enable/disable LT, Configurable Restart, Burn In Initialization Mode, Disable Hyper Threading, System BSP Socket Indication, and Platform Topology Index.

Method, system, and apparatus for system level initialization by conveying capabilities and identifiers of components

Systems and methods for error handling are disclosed. The systems and methods may be utilized for single or multiple processor computer systems to handle errors in a coordinated manner between hardware and any firmware or software layers. A computer system includes a non volatile memory and at least one processor. A firmware error handling routine is stored on the non volatile memory. The firmware error handling routine is for handling errors. Each of the at least one processors detects errors. Each processor executes the firmware error handling routine on detecting an error. The executed firmware error handling routine handles the error. The executed firmware error handling routine also logs error information to a log. The systems and methods provide for coordinated error handling that enhance error recovery, provide error containment and maintain system availability.

System abstraction layer, processor abstraction layer, and operating system error handling

Method, system, and apparatus for system level initialization

A system comprises a non volatile memory and a plurality of processors. The non volatile memory stores an error handling routine. Each processor of the plurality of processors accesses the error handling routine on detecting an error and, on certain errors, signals the remaining processors to enter a rendezvous state. In the rendezvous state, a single processor takes over and performs error handling.

Error correction apparatus, systems, and methods

An embodiment of the present invention is a technique to process system management interrupt. A system management interrupt (SMI) is received. The SMI is associated with a system management mode (SMM). A conditional SMI inter-processor interrupt (IPI) message is broadcast to at least a processor. The SMI is processed without waiting for the at least processor to check into the SMM. A clear pending SMI is broadcast to the processors at end of SMI processing to clear a pending SMI condition.

Conditional and vectored system management interrupts

A firmware-based mechanism for creating, storing and retrieving variable-length records associated with error events occurring in a computer platform. The mechanism responds to error notifications by invoking a firmware-based error-handling module. The error-handling module retrieves processor-specific error information and may also interrogate the other components of the computer platform to determine their error status. Then, according to the nature of the discovered errors, the error-handling module may assemble the retrieved error information and status information into a variable-length error record, which the error-handling module may then store in a memory. On request from a processing agent, the error-handling module may retrieve a previously-stored error record and present it to the requesting agent. Thus, the invention provides a unified and standardized approach to computer error handling at the firmware level.

Scalable CPU error recorder

Algorithm for non-volatile memory updates

Rendezvous of processors with OS coordination

A mechanism is provided for booting a computer system that is capable of implementing different instruction set architectures, through a network. An embodiment of the invention includes a network controller implemented for a first ISA and a processor capable of implementing programs written in a second ISA as well as programs written in the first ISA. Following preliminary boot operations provided through non-volatile system memory, a network boot program provided by the network controller is implemented. The boot program requests the non-volatile system memory for an indication of the operating system to be loaded and generates a boot request for the indicated operating system. When the indicated operating system is written in the second ISA, the boot program loads the OS to a specified location in system memory and sends the processor into a mode suitable for executing the second ISA.

Mechanism for booting a computer through a network

Growing community of inventors

Cupertino, CA, United States of America

Mani Ayyar