Lg Display Co., Ltd.

Mangyu Park

Yangseok Jeong

JinCheol Hong

Pilsung Kang

Geunwoo Koh

Soondong Cho

Jeongho Kang

Hyunchul Kim

Changhun Cho

Jincheol Hong

Seungcheol Oh

A liquid crystal display comprises: a first data drive circuit that supplies a data voltage to data lines present in a first portion and a third portion on the screen of a liquid crystal display panel in response to a first source output enable signal; and a second data drive circuit that supplies the data voltage to data lines present in a second portion and a fourth portion on the screen of the liquid crystal display panel in response to a second source output enable signal. The first source output enable signal controls the data voltage output timing and charge sharing timing of the first data drive circuit. The second source output signal controls the data output timing and charge sharing timing of the second data drive circuit in a different way from the first data drive circuit.

Liquid crystal display

A disclosed display device includes a display panel with data lines and gate lines, the gate lines including odd-numbered gate lines and even-numbered gate lines. The display device also includes a timing controller to generate a gate output enable signal, and a gate output enable signal division circuit to extract odd-numbered high logic periods of the gate output enable signal to output a first gate output enable signal and to extract even-numbered high logic periods of the gate output enable signal to output a second gate output enable signal. The display device further includes a gate driver to supply a first gate pulse to an odd-numbered gate line in response to the first gate output enable signal and a second gate pulse to an even-numbered gate line in response to the second output enable signal.

Display device and driving method thereof

A liquid crystal display including a liquid crystal display panel including a plurality of data lines, a plurality of gate lines intersecting the data lines, and liquid crystal cells respectively formed at intersections of the data lines and the gate lines, and divided into a first area, a second area and a third area, a first data integrated circuit (IC) that drives the first area, a second data IC that drives the second area, a third data IC that drives the third area, and a timing controller that analyzes an input digital video data, generates a first selection signal and a second selection signal for controlling whether charge sharing is used, and independently controls the first, second, and third data ICs using the first and second selection signals, wherein the second area is divided into a first block adjoining the first area, a third block adjoining the third area and a second block located between the first block and the third block; and the first selection signal controls whether the charge sharing is used for the first and third data ICs, and the second selection signal controls whether the charge sharing is used for the second block and controls a charging delay variation so that the charging delay variation is lessened between the second block and the first area or between the second block and the third area in the first or third block.

A liquid crystal display and a method of driving the same are disclosed. The liquid crystal display includes a timing controller, N source drive integrated circuits (ICs), where N is an integer equal to or greater than 2, N pairs of data bus lines, each of which connects the timing controller to each of the N source drive ICs in a point-to-point manner, a lock check line that connects a first source drive IC of the N source drive ICs to the timing controller and cascade-connects the N source drive ICs to one another, and a feedback lock check line connecting a last source drive IC of the N source drive ICs to the timing controller. A swing width of an output voltage of the timing controller increases in proportion to a distance between the timing controller and the N source drive ICs.

Liquid crystal display and method of driving the same

A liquid crystal display and a method of driving the same are provided. The liquid crystal display includes a timing controller, N source drive integrated circuits (ICs), where N is an integer equal to or greater than 2, N pairs of data bus lines, each of which connects the timing controller to each of the N source drive ICs in a point-to-point manner, a lock check line that connects a first source drive IC of the N source drive ICs to the timing controller and cascade-connects the N source drive ICs to one another, and a feedback lock check line that connects a last source drive IC of the N source drive ICs to the timing controller.

A liquid crystal display and a method of driving the same are disclosed. The liquid crystal display includes a timing controller, N source drive integrated circuits (ICs), where N is an integer equal to or greater than 2, N pairs of data bus lines, each of which connects the timing controller to each of the N source drive ICs in a point-to-point manner, a lock check line that connects a first source drive IC of the N source drive ICs to the timing controller and cascade-connects the N source drive ICs to one another, and a feedback lock check line that connects a last source drive IC of the N source drive ICs to the timing controller.

Growing community of inventors

Seoul, South Korea

Mangyu Park