Neomagic Corporation

Mangesh S Pimpalkhare

Chester F Bassetti

Andrew Rosman

Krishnan C Dharmarajan

Hung-Sung Li

A 3D-graphics engine has several texture maps with different levels of detail (LOD). The largest of the four derivatives of the u,v texture-map coordinates with respect to the x,y screen coordinates determines which LOD texture map to select. Using bi-linear interpolation, the four nearest texture pixels or texels are fetched from the texture map in a texture memory and a weighted-average texel generated. Distortion in space and time can be visible when a triangle transitions from one LOD texture map to the next LOD map. Tri-linear interpolation eliminates this LOD-transitioning distortion by generating weighted-average texels for both the LOD map and for four texels from a next LOD map. Unfortunately the calculational complexity is more than doubled for tri-linear rather than bi-linear interpolation. Tri-linear interpolation is employed only near a transition to a next LOD map. When the derivatives are not near an LOD-map transition, only bi-linear interpolation is performed. When the derivatives are near the LOD transition, tri-linear interpolation smoothes out the transition, eliminating visible distortions. The tri-linear interpolation performs linear LOD-blending with various slopes larger than typical, or with a non-linear blending function read from a lookup table. An interpolation factor read from the lookup table or generated by shifting the LOD fraction is multiplied by the weighted-texel average for the tri-linear weighting.

Texture map blender with adaptive interpolation when switching to a new level-of-detail map

Adaptive tri-linear interpolation for use when switching to a new level-of-detail map

A graphics controller uses spread-spectrum techniques to modulate the pixel clock over a range of frequencies, reducing the maximum intensity of EMI emissions. When the clock input to the graphics controller is replaced with a modulated clock, the image on a CRT is distorted. Distortion is avoided by only modulating the clock to the flat-panel LCD interface. The vertical and horizontal timing signals for both the CRT and the LCD are generated from the un-modulated clock. Using the un-modulated clock for these critical timing signals ensures that each horizontal line is displayed for the same period of time. Brighter and dimmer lines are thus avoided. A second embodiment modulates the clocks to the CRT and LCD, reducing emissions for both interfaces. Even the timing signals use the modulated clock. The frequency sweep of the modulated clock is reset at the end of every horizontal line. Thus all lines are displayed for the same period, although the transfer of pixels within a line are modulated. Even though the pixel clock is modulated while pixels are written to the displays, the same sequence of modulations is repeated for each line. Thus pixels from different lines are aligned and zig-zag and wiggle distortions seen when simple asynchronous modulation is applied to all clocks is avoided.

EMI reduction for a flat-panel display controller using

A clock generator produces a frequency-modulated clock. A master phase-locked loop (PLL) includes a voltage summer that outputs a voltage to a voltage-controlled oscillator (VCO). The voltage to the VCO determines the frequency of the clock generated. A modulated voltage is subtracted by the voltage summer to produce voltage and thus frequency modulations. This modulated voltage is produced by a second loop that operates as a slave to the master PLL. The slave loop is a voltage-locked loop. The peak amplitude of the modulated voltage is locked to a control voltage of the master PLL. The control voltage is a stable voltage input to the voltage summer that is generated by phase comparisons of the output clock to a reference clock. To overcome the problem of locking to the modulating output clock, phase comparison is performed only at the same point in the modulation cycle, at the beginning of each modulation cycle. Thus modulations do not affect phase comparisons. The modulated voltage is generated by a waveform generator in the slave loop. The waveform generator is controlled by a feedback divider that also controls when phase comparison is performed. The amplitude of the waveform is adjusted to track the control voltage of the master PLL by comparing the control voltage to the modulated voltage, but only at the beginning of the modulation cycle. The modulation amplitude is kept constant over different supply voltages, ambient temperatures, and process corners.

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Santa Clara, CA, United States of America

Mangesh S Pimpalkhare