Applied Materials, Inc.

Mangesh Bangar

Huixiong Dai

Srinivas D Nemani

Ellie Y Yieh

Christopher S Ngai

Steven Hiloong Welch

Dmitry Lubomirsky

Abhilash J Mayur

Bruce E Adams

Kelly E Hollar

Jaujiun Chen

Douglas A Buchberger, Jr

Steve G Ghanayem

Alan Tso

Gautam Pisharody

Christopher Siu Wing Ngai

Liyan Miao

Lancelot Huang

A method for processing a substrate is described. The method includes forming a metal containing resist layer onto a substrate, patterning the metal containing resist layer, and performing a post exposure bake on the metal containing resist layer. The post exposure bake on the metal containing resist layer is a field guided post exposure bake operation and includes the use of an electric field to guide the ions or charged species within the metal containing resist layer. The field guided post exposure bake operation may be paired with a post development field guided bake operation.

Metal oxide resist patterning with electrical field guided post-exposure bake

A method for enhancing a photoresist profile control includes applying a photoresist layer comprising a photoacid generator on an underlayer disposed on a material layer, exposing a first portion of the photoresist layer unprotected by a photomask to light radiation in a lithographic exposure process, providing a thermal energy to the photoresist layer in a post-exposure baking process, applying an electric field or a magnetic field while performing the post-exposure baking process, and drifting photoacid from the photoresist layer to a predetermined portion of the underlayer under the first portion of the photoresist layer.

Photoresist patterning process

A method for enhancing the depth of focus process window during a lithography process includes applying a photoresist layer comprising a photoacid generator on a material layer disposed on a substrate, exposing a first portion of the photoresist layer unprotected by a photomask to light radiation in a lithographic exposure process, providing a thermal energy to the photoresist layer in a post-exposure baking process, applying an electric field or a magnetic field while performing the post-exposure baking process, and dynamically changing a frequency of the electric field as generated while providing the thermal energy to the photoresist layer.

Lithography process window enhancement for photoresist patterning

Methods and apparatuses for minimizing line edge/width roughness in lines formed by photolithography are provided. In one example, a method of processing a substrate includes applying a photoresist layer comprising a photoacid generator to on a multi-layer disposed on a substrate, wherein the multi-layer comprises an underlayer formed from an organic material, inorganic material, or a mixture of organic and inorganic materials, exposing a first portion of the photoresist layer unprotected by a photomask to a radiation light in a lithographic exposure process, and applying an electric field or a magnetic field to alter movement of photoacid generated from the photoacid generator substantially in a vertical direction.

Film structure for electric field guided photoresist patterning process

Embodiments of the present disclosure generally relate to apparatus and methods for verification and re-use of process fluids. The apparatus generally includes a tool for performing lithography, and a recirculation path coupled to the tool. The recirculation path generally includes a collection unit coupled at first end to a first end of the tool, and a probe coupled at a first end to a second end of the collection unit, the probe for determining one or more characteristics of a fluid flowing from the tool. The recirculation path of the apparatus further generally includes a purification unit coupled at a first end to a third end of the collection unit, the purification unit further coupled at a second end to a second end of the probe, the purification unit for changing a characteristic of the fluid.

Apparatus and methods for verification and re-use of process fluids

Embodiments disclosed herein relate to methods and systems for correcting overlay errors on a surface of a substrate. A processor performs a measurement process on a substrate to obtain an overlay error map. The processor determines an order of treatment for the substrate based on the overlay error map. The order of treatment includes one or more treatment processes. The processor generates a process recipe for a treatment process of the one or more treatment processes in the order of treatment. The processor provides the process recipe to a substrate treatment apparatus.

Hybrid laser and implant treatment for overlay error correction

A calibration curve for a wafer comprising a layer on a substrate is determined. The calibration curve represents a local parameter change as a function of a treatment parameter associated with a wafer exposure to a light. The local parameter of the wafer is measured. An overlay error is determined based on the local parameter of the wafer. A treatment map is computed based on the calibration curve to correct the overlay error for the wafer. The treatment map represents the treatment parameter as a function of a location on the wafer.

Overlay error correction

Methods of laterally oxidizing features of a patterned substrate are described. A capping layer may be disposed above lateral features to laterally confine the oxidation. The oxidizable features may be material patterned near the optical resolution of a photolithography system using a high-resolution photomask. The oxidizable features may be wider than the spaces between the oxidizable features and may be about three times the width of the spaces. Oxidized portions may be formed on either side of repeated oxidizable features. The unoxidized portions may then be removed as part of a self-aligned double patterning (SADP) process. A gapfill layer deposited thereon may be etched or polished back to form alternating fill and non-sacrificial features.

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San Jose, CA, United States of America

Mangesh Bangar