Infineon Technologies Ag

Other

Siemens Aktiengesellschaft

Infineon Technologies Austria Ag

Qimonda Ag

Infineon Technologies LLC

Technische Universitaet Graz

Manfred Schneegans

Bernhard Weidgans

Michael Roesner

Martin Mischitz

Franziska Haering

Markus Heinrici

Werner Kroeninger

Hans-Joachim Schulze

Markus Zundel

Ivan Nikitin

Edmund Riedl

Michael Rogalli

Holger Torwesten

Michael Pinczolits

Andreas Peter Meiser

Alexander Heinrich

Stefan Krivec

Karsten Guth

Holger Huebner

Sokratis Sgouridis

Barbara Eichinger

Werner Kröninger

David Wallis

Markus Leicht

Dirk Mueller

Anton Mauder

Thorsten Meyer

Joachim Mahler

Khalil Hosseini

Stefan Dietrich

Georg Meyer-Berg

Carsten Ahrens

Peter Irsigler

Irmgard Escher-Poeppel

Wolfgang Lehnert

Adolf Koller

Gudrun Stranzl

Friedrich Kroener

Werner Robl

Evelyn Napetschnig

Oliver Hellmund

Stephan Wege

Stefan Woehlert

Gerald Lackner

Johann Gatterbauer

Thomas Peter Haneder

Peter Scherl

Franco Mariani

Alexander Ruf

Johannes Lodermeyer

Rainer Pelzer

Kurt Matoy

Michael Melzl

Grit Sommer

Reinhard Pufall

Magdalena Hoier

Hannes Eder

Ulrike Bewersdorff-Sarlette

Ivan Galesic

Caterina Travan

Florian Binder

Jürgen Förster

Frank Pietzschmann

Klaus Schmidt

Patrick Schwarz

Lothar Koenig

Jens Goerlich

Werner Kroninger

Wolfgang Jäger

Wolfgang Jaeger

Alexander Hirsch

Judith Lehmann

Stefan Wohlert

A method of forming an aluminum oxide layer is provided. The method includes providing a metal surface including at least one metal of a group of metals, the group of metals consisting of copper, aluminum, palladium, nickel, silver, and alloys thereof. The method further includes depositing an aluminum oxide layer on the metal surface by atomic layer deposition, wherein a maximum processing temperature during the depositing is 280&#xb0; C., such that the aluminum oxide layer is formed with a surface having a liquid solder contact angle of less than 40&#xb0;.

Method of forming an aluminum oxide layer, metal surface with aluminum oxide layer, and electronic device

A power semiconductor device includes a semiconductor body configured to conduct a load current. A load terminal electrically connected with the semiconductor body is configured to couple the load current into and/or out of the semiconductor body. The load terminal includes a metallization having a frontside and a backside. The backside interfaces with a surface of the semiconductor body. The frontside is configured to interface with a wire structure having at least one wire configured to conduct at least a part of the load current. The frontside has a lateral structure formed at least by at least one local elevation of the metallization. The local elevation has a height in an extension direction defined by a distance between the base and top of the local elevation and, in a first lateral direction perpendicular to the extension direction, a base width at the base and a top width at the top.

Terminal structure of a power semiconductor device

A metallic interconnection and a semiconductor arrangement including the same are described, wherein a method of manufacturing the same may include: providing a first structure including a first metallic layer having protruding first microstructures; providing a second structure including a second metallic layer having protruding second microstructures; contacting the first and second microstructures to form a mechanical connection between the structures, the mechanical connection being configured to allow fluid penetration; removing one or more non-metallic compounds on the first metallic layer and the second metallic layer with a reducing agent that penetrates the mechanical connection and reacts with the one or more non-metallic compounds; and heating the first metallic layer and the second metallic layer at a temperature causing interdiffusion of the first metallic layer and the second metallic layer to form the metallic interconnection between the structures.

Metallic interconnect, a method of manufacturing a metallic interconnect, a semiconductor arrangement and a method of manufacturing a semiconductor arrangement

An electrolyte may be provided. The electrolyte may include at least one additive configured to decompose or evaporate at a temperature above approximately 100&#xb0; C., and a water soluble metal salt, and the electrolyte may be free from carbon nanotubes. In various embodiments, a method of forming a metal layer may be provided: The method may include depositing a metal layer on a carrier using an electrolyte, wherein the electrolyte may include at least one additive configured to decompose or evaporate at a temperature above approximately 100&#xb0; C. and a water soluble metal salt, wherein the electrolyte is free from carbon nanotubes; and annealing the metal layer to form a metal layer comprising a plurality of pores. In various embodiments, a semiconductor device may be provided. The semiconductor device may include a metal layer including a plurality of pores, wherein the plurality of pores may be formed in the metal layer as remnants of an additive having resided in the plurality of pores and having at least partially decomposed or evaporated. To keep a high elasticity over a wide temperature range (up to 450&#xb0; C.), an adhesion layer may stabilize the metal grain boundaries and may fix dislocation gliding inside metal grains. In various embodiments, a metal layer is provided. The metal layer may include a plurality of pores having ellipsoidal or spheroidal shape.

Electrolyte, method of forming a copper layer and method of forming a chip

A method of manufacturing a semiconductor device includes forming a semiconductor substrate that has a conductive structure, and forming a precursor auxiliary layer stack on a first section of the conductive structure. The precursor auxiliary layer stack has a precursor adhesion layer and a precursor barrier layer between the precursor adhesion layer and the conductive structure. The precursor adhesion layer contains a second metal. The method further includes forming, on the precursor auxiliary layer stack, a metal structure containing a first metal and forming, from portions of the precursor auxiliary layer stack an adhesive layer containing the first and second metals.

Semiconductor device with metal structure electrically connected to a conductive structure

According to various embodiments, a method for processing a substrate may include: processing a plurality of device regions in a substrate separated from each other by dicing regions, each device region including at least one electronic component; wherein processing each device region of the plurality of device regions includes: forming a recess into the substrate in the device region, wherein the recess is defined by recess sidewalls of the substrate, wherein the recess sidewalls are arranged in the device region; forming a contact pad in the recess to electrically connect the at least one electronic component, wherein the contact pad has a greater porosity than the recess sidewalls; and singulating the plurality of device regions from each other by dicing the substrate in the dicing region.

Method of processing a porous conductive structure in connection to an electronic component on a substrate

In various embodiments, a die is provided. The die may include a die body, and at least one of a front side metallization structure on a front side of the die body and a back side metallization structure on a back side of the die body such that the die is plane or includes a positive radius of curvature at a die attach process temperature range.

Method for processing a die

A semiconductor device includes a semiconductor die that having a conductive structure. A metal structure is electrically connected to the conductive structure and contains a first metal. An auxiliary layer stack is sandwiched between the conductive structure and the metal structure and includes an adhesion layer that contains a second metal. The auxiliary layer stack further includes a metal diffusion barrier layer between the adhesion layer and the conductive structure. The adhesion layer contains the first metal and a second metal.

A method of manufacturing a layer structure includes: forming a first layer over a substrate; planarizing the first layer to form a planarized surface of the first layer; and forming a second layer over the planarized surface; wherein a porosity of the first layer is greater than a porosity of the substrate and greater than a porosity of the second layer; wherein the second layer is formed by physical vapor deposition; and wherein the first layer and the second layer are formed from the same solid material.

Method of manufacturing a layer structure having partially sealed pores

A method for forming a semiconductor device includes forming device regions in a semiconductor substrate having a first side and a second side. The device regions are formed adjacent the first side. The method further includes forming a seed layer over the first side of the semiconductor substrate, and forming a patterned resist layer over the seed layer. A contact pad is formed over the seed layer within the patterned resist layer. The method further includes removing the patterned resist layer after forming the contact pad to expose a portion of the seed layer underlying the patterned resist layer, and forming a protective layer over the exposed portion of the seed layer.

Source down semiconductor devices and methods of formation thereof

A method for fabricating a semiconductor device includes forming a conductive liner over a first landing pad in a first region and over a second landing pad in a second region. The method further includes depositing a first conductive material within first openings within a resist layer formed over the conductive liner. The first conductive material overfills to form a first pad and a first layer of a second pad. The method further includes depositing a second resist layer over the first conductive material, and patterning the second resist layer to form second openings exposing the first layer of the second pad without exposing the first pad. A second conductive material is deposited over the second layer of the second pad.

Multi-layer metal pads

Various embodiments provide a method of forming a bondpad, wherein the method comprises providing a raw bondpad, and forming a recess structure at a contact surface of the raw bondpad, wherein the recess structure comprises sidewalls being inclined with respect to the contact surface.

Method of forming a bondpad and bondpad

In accordance with an alternative embodiment of the present invention, a method for forming a semiconductor device includes applying a paste over a semiconductor substrate, and forming a ceramic carrier by solidifying the paste. The semiconductor substrate is thinned using the ceramic carrier as a carrier.

Carrier system for processing semiconductor substrates, and methods thereof

A method of manufacturing an electronic device may include: forming at least one electronic component in a substrate; forming a contact pad in electrical contact with the at least one electronic component; wherein forming the contact pad includes: forming a first layer over the substrate; planarizing the first layer to form a planarized surface of the first layer; and forming a second layer over the planarized surface, wherein the second layer has a lower porosity than the first layer.

Method of manufacturing an electronic device having a contact pad with partially sealed pores

Growing community of inventors

Vaterstetten, Germany

Manfred Schneegans