Infineon Technologies Ag

Manfred Pröll

Stephan Schröder

Jörg Kliewer

Ralf Schneider

Herbert Benzinger

Georg Erhard Eggers

Koen Van Der Zanden

Jürgen Auge

Joerg Vollrath

Manfred Dobler

Christian Stocken

Aurel Von Campenhausen

Thomas Huber

Evangelos Stavrou

Gerald Resch

Johann Pfeiffer

Arndt Gruber

Gerrit Färber

Frank Schroeppel

Claus Engelhardt

Nazif Taskin

Björn Wirker

Heinz-Joachim Neubauer

Semiconductor memories () have segmented word lines (), which in each case have a main word line () made of a conductive metal and a plurality of interconnect segments () coupled to the main word line (), which are coupled to the respective main word line () in each case via at least one contact hole filling (). If one of the contact hole fillings () is defective or at high resistance then functional errors of the semiconductor memory occur. The interconnect segments () of two respective word lines () can be short-circuited in pairs with the aid of switching units (), whereby a static current (I) that flows via the contact hole fillings () can be used for electrically stressing the contact hole fillings (). Electrical stressing of contact hole fillings of segmented word lines is thus made possible.

Integrated semiconductor memory and method for electrically stressing an integrated semiconductor memory

An integrated semiconductor memory device includes at least one memory cell, at least one sense amplifier and a pair of bit lines connected to each sense amplifier, where each memory cell includes a selection transistor and a storage capacitor. The storage capacitor of each memory cell includes a first capacitor electrode and a second capacitor electrode, and the selection transistor of each memory cell includes a first source/drain region that is connected by a first contact connection to one bit line of a pair of bit lines corresponding with the memory cell, and a second source/drain region that is conductively connected to the first capacitor electrode of the storage capacitor of the memory cell. The second capacitor electrode of the storage capacitor of each memory cell is connected to the other bit line of the pair of bit lines corresponding with the memory cell.

Integrated semiconductor memory and method for operating a semiconductor memory

An integrated semiconductor memory includes word lines connected to a first voltage potential via a respective first controllable switch and a respective third controllable switch and to a second voltage potential via a respective second controllable switch. In order to test whether one of the word lines is connected to the first voltage potential via its respective first and third controllable switches, the one of the word lines is connected to a comparator circuit via the respective second controllable switch and a driver line. After the respective first and third controllable switches have been controlled into the on state, in a test operating state of the integrated semiconductor memory, the respective second controllable switch is controlled into the on state and a potential state on the word line is evaluated by the comparator circuit. The result of the evaluation is fed to an external data terminal by an evaluation signal.

Integrated semiconduct memory with test circuit

An integrated circuit, in particular, an integrated memory, contains a control circuit for ascertaining an operating state of the circuit. A self-repair circuit, which is connected to the control circuit, is used to implement self-test and self-repair operation for checking the functioning of, and repairing, defective circuit sections of the integrated circuit. After a supply voltage has been applied to the integrated circuit, the control circuit ascertains an operating state of the integrated circuit and, in a manner dependent thereon, the self-repair circuit is activated by the control circuit in a self-controlling manner in order to put the integrated circuit into a self-repair mode for implementing self-test and self-repair operation. The integrated circuit can be tested for its functionality and repaired even after being soldered onto a module substrate.

Integrated circuit, in particular integrated memory, and methods for operating an integrated circuit

A circuit arrangement can have a number of integrated circuit components, which are arranged on a carrier substrate. A reception circuit for receiving a control signal can be coupled to one of the connection pads on the input side and can be connected to each of the circuit components on the output side. A bridging circuit controlled by a test mode signal can electrically bridge the reception circuit. In a testing method, a plurality of connection pads can be connected to a first potential and at least one of the connection pads can be connected to a second potential. The bridging circuit can be activated and the current measured, by a test arrangement, at the at least one of the connection pads. Inspection for leakage currents in connections between input-side reception circuits and the circuit components can be measured.

Circuit arrangement having a number of integrated circuit components on a carrier substrate and method for testing a circuit arrangement of this type

An integrated semiconductor memory including memory cells which can be driven via first and second word lines and can be replaced by redundant memory cells. In the first memory cell type, data can be stored corresponding to the data present at a data input terminal. In the memory cells of a second memory cell type, data can be stored inverted with respect to data present at the data input terminal. The integrated semiconductor memory includes a circuit for data inversion, wherein the data are written to a redundant memory cell, inverted with respect to the data present at the data input terminal if the defective memory cell and the redundant memory cell replacing it are situated in different word line strips of a bit line twist, and if the defective memory cell and the redundant memory cell replacing it are associated with different memory cell types.

Integrated semiconductor memory with redundant memory cells replaceable for either true or complementary defective memory cells

An integrated semiconductor memory includes a memory cell array with at least one memory cell, in which a data value is stored, and an evaluation circuit with a counter. During a test of the integrated semiconductor memory, a counter reading of the counter is altered if the data value stored in the memory cell deviates from a desired value. A threshold value is predefined by a control circuit. A programming circuit compares the threshold value on the input side with the instantaneous counter reading of the counter. If the counter reading of the counter exceeds the threshold value, a programming element changes from a first programming state to a second programming state. After the conclusion of the test, the state of the programming element is read out via an output terminal. This scheme makes it possible to deduce a possible cause of failure of the integrated semiconductor memory.

Integrated semiconductor memory

In an arrangement for determining a temperature loading during a soldering process, a semiconductor chip () comprises at least one contact () to be soldered or is electrically conductively connected to at least one contact () to be soldered that is situated outside the semiconductor chip. The semiconductor chip () furthermore comprises a temperature sensor device (), which determines a measurement quantity corresponding to the temperature. A processing device () has an analog-to-digital converter (), which is electrically conductively connected to the temperature sensor device () and converts the measurement quantity into at least one storable signal that represents the temperature loading. A voltage supply device (), which is electrically conductively connected to the temperature sensor device () and the processing device (), supplies these components with an operating voltage. A data memory () serves for storing the at least one storable signal. An electrical line () connected to the data memory () serves for outputting the stored signal. As a result, it is possible to monitor temperature loadings of the semiconductor chip also outside the sphere of influence of the semiconductor manufacturer.

Arrangement for determining a temperature loading of an integrated circuit and method

An integrated circuit includes an input terminal (IN) for application of a supply voltage (Vext) and an output terminal (A) for generation of an output voltage (Vout). A first branch including a first controllable resistance (T) and a second branch including a charge pump () and a second controllable resistance (T) are connected between the input terminal (IN) and the output terminal (A). A control circuit () alters the resistance values of the first and second controllable resistances (T, T) in a manner dependent on a ratio of an actual value (Vout) of the output voltage to a desired value (VSout) of the output voltage and a ratio of an actual value (Vext) of the supply voltage to a desired value (VSext) of the supply voltage. As a result, the output voltage (Vout) can be stabilized to the desired value (VSout) virtually independently of fluctuations of the supply voltage.

Integrated circuit for stabilizing a voltage

An integrated chip has a clock signal input () for application of a first clock signal (clk) and a clock signal output (). Moreover, it has a phase locked loop (), which, on the input side, is connected to the clock signal input () and serves far generating a second clock signal (clk). Furthermore, the chip has a multiplexer (MUX), via which the first clock signal (clk) or the second clock signal (clk) can optionally be switched to the clock signal output (), and a unit for frequency monitoring (), which, on the input side, is connected to the clock signal input () and is designed and can be operated in such a way that, in the event of a limiting frequency (fmin) being undershot, the multiplexer (MUX) is caused to switch the first clock signal (clk) to the clock signal output ().

Integrated clock supply chip for a memory module, memory module comprising the integrated clock supply chip, and method for operating the memory module under test conditions

An integrated memory has individually addressable normal and redundant units of memory cells. A memory unit is used to store, in a normal mode, an address for one of the normal units which needs to be replaced by one of the redundant units. A comparison unit compares an address which is present on an address bus with an address stored in the memory unit and activates one of the redundant units in the event of a match being identified. The memory also has a test circuit which can be activated by a test mode signal, can reset the memory unit to an initial state, and can store an address for one of the redundant units in the memory unit for subsequently writing an identification code to this redundant unit.

Integrated memory having redundant units of memory cells and method for testing an integrated memory

An integrated semiconductor memory includes at least one word line and a number of memory cells. Each memory cell has a selection transistor coupled to the word line. A word line driver is coupled to the word line. The word line driver provides a first electrical potential or a second electrical potential to the word line such that the word line is activated by the first electrical potential and is deactivated by the second electrical potential. A passive component (e.g., a diode or a resistor) is coupled between the word line and the second electrical potential such that the word line is coupled to the second electrical potential in a high-resistance fashion through the passive component. The passive component is transmissive for a leakage current between the word line and the contact connection.

Integrated semiconductor memory comprising at least one word line and comprising a multiplicity of memory cells

An integrated semiconductor memory can be operated in a normal operating state synchronously with a control clock. In the test operating state, the integrated semiconductor memory is driven synchronously with a clock edge of the control clock with a first control signal and starts a test run independent of the control clock. Driving with the first control signal, selection transistors in a memory bank that can be selected by a memory bank address are turned off. Afterward, bit lines in the selected memory bank are interconnected and driven with a predetermined precharge potential. After a precharge time has elapsed, one of the word lines is selected by an applied word line address and the selection transistors in the selected memory bank connected to the selected word line are turned on. Precharge times are set and tested independently of the clock period of the control clock.

Method for testing an integrated semiconductor memory

An integrated semiconductor memory device includes a memory cell array (B) with a first bit line and a second bit line (BL, /BL), a controllable resistor (SW) and a control unit () configured to control the controllable resistor. In a first operating state of the integrated semiconductor memory device, the first and second bit lines are connected to one another via a first controllable switch (ET) and also via the controllable resistor (SW) which has been set to a low resistance, to a connection (A) that applies a mid-voltage (V), where the voltage level of the mid-voltage is in the form of an arithmetic mean between a first and second voltage potential (VBLH, VBLL). By virtue of the control unit briefly setting the controllable resistor to a very low resistance in the first operating state of the integrated semiconductor memory device, the period of time required for the first and second bit lines require to assume the mid-voltage (V) is shortened. The influence of capacitive coupling influences, which slow down the charging of the first and second bit lines to the mid-voltage, is significantly reduced as a result.

Integrated semiconductor memory device and method for operating an integrated semiconductor memory device

A circuit for controlling an access to an integrated memory includes a command decoder for receiving at least one external command for an access to the memory. An access controller is connected to the command decoder for receiving internal command signals, which are output by the command decoder. In the course of a memory access, the command decoder outputs a precharge command signal for precharging a row of the memory cell array of the integrated memory. A control circuit, which can determine a temperature of the memory, is designed to temporally variably influence the transmission of the precharge command signal of the command decoder to the access controller in a manner dependent on the temperature of the memory. The write recovery time tWR can be retained even for higher operating frequencies of the memory.

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Dorfen, Germany

Manfred Pröll