Infineon Technologies Ag

Qimonda Ag

Manfred Proell

Stephan Schroeder

Joerg Kliewer

Herbert Benzinger

Ralf Schneider

Wolfgang Ruf

Aurel Von Campenhausen

Manfred Dobler

Marcin Gnat

Georg Erhard Eggers

Koen Van Der Zanden

Arndt Gruber

Hermann Haas

Hermann Hass

An apparatus and methods for testing an integrated device comprising memory a test device are provided. At least two data inputs of the memory are coupled to a data output of the test device. As an alternative, at least two data outputs of the memory are coupled to a data input of the test device. Test data are transferred from the test device to the memory chip and written to memory cells of the memory. Data are read from the memory cells of the memory and transferring from the memory to the test device. The data read from the memory chip are compared with the test data written to the memory in order to identify faults of the memory.

Method and apparatus for testing a memory chip using a common node for multiple inputs and outputs

An integrated device comprises a functional circuit, a test circuit for testing the functional circuit and for providing an error data item and a register element for storing the error data item and for outputting the error data item at an error data output of the integrated device responsive to an output signal. The register element is connected to a data input of the integrated device in order to accept a data item, which is applied to the data input, responsive to the output signal.

Integrated device for simplified parallel testing, test board for testing a plurality of integrated devices, and test system and tester unit

A device can be used for refreshing memory contents of first and second memory cells. The memory contents of the first memory cells are refreshed in a first period of time and the memory contents of the second memory cells are refreshed in a second period of time. A pre-charge circuit is provided for bit lines for the first memory cells and the second memory cells. A controller may be coupled to the pre-charge circuit to control the pre-charge circuit such that a pre-charge voltage may be applied to the bit lines of the first memory cells during the first period of time and not during the second period of time and that the pre-charge voltage may be applied to the bit lines of the second memory cells during the second period of time and not during the first period of time.

Device for refreshing memory contents

A method for improving the reliability of a memory having a used memory region and an unused memory region, wherein defect memory elements in the used memory region can be substituted by functional memory elements in the unused memory region, having the steps of providing the used memory region with a first stress sequence; and providing the unused memory region with a second stress sequence.

Memory and method for improving the reliability of a memory having a used memory region and an unused memory region

A semiconductor memory and a method for operating the latter in order are provided, at least in testwise fashion, to deactivate a word line segment () of a segmented word line not via a first line () otherwise used for deactivation, but rather via a second line () via that the word line segment () is otherwise activated. The second line () can optionally be biased with a second potential (Vpp) provided for activation or with a third potential (Vgnd). If the third potential (Vgnd) is used for at least temporarily deactivating the word line segment (), the word line segment can be driven via a switching element (), which couples the word line segment to the second line (), without the complementary switching element () of the driver segment () having to be used for deactivation. It can thereby be ascertained which of two switching elements () of the driver segment is defective and whether or not the semiconductor memory will function in a manner free of errors after permanent replacement of the word line on account of a floating potential of the tested word line segment ().

Integrated semiconductor memory and method for operating an integrated semiconductor memory

A semiconductor memory and a test method for testing whether word line segments () are floating after an activation operation or a deactivation operation is disclosed. For this purpose, the charge-reversal current (I) that occurs in the event of a word line segment () being subjected to charge reversal or a charge quantity (Q) which is fed to the word line () or conducted away from the word line segment () as a result of this is measured. If, upon activation or deactivation of a word line segment (), the measured charge-reversal current (I) or the corresponding charge quantity (Q) is less than a lower limit value, it is ascertained that the relevant word line segment () has a defective contact terminal. In this way, high-impedance or defective contact hole fillings can thereby be identified and the associated word line segments () can be replaced by redundant word lines.

Integrated semiconductor memory comprising at least one word line and method

A semiconductor memory includes storage cells () that have storage capacitors and transistors with an electrode, which is electrically biasable with two different electrical potentials (VV) in order to open and close the transistor. The electrode potential (V) intended for the off state of the transistor is a temperature-dependent potential, the value of which is controlled temperature-dependently by the semiconductor memory () so that the second electrical potential (V) becomes more different from the first electrical potential (V) as the temperature (T) increases.

Semiconductor memory and method for operating a semiconductor memory

The invention relates to a RAM store having a shared SA structure, in which sense amplifiers (SA) arranged in SA strips () between two respective adjacent cell blocks are used by a plurality of bit line pairs () from the adjacent cell blocks and the bit line pairs () have respective charge equalization circuits individually associated with them for the purpose of performing charge equalization between the bit line halves of the bit line pairs () in a precharge phase, where a shorting transistor () is provided which, when prompted by a control signal (EQLx), connects the bit line halves (BLT, BLC) of the bit line pairs () which are in the precharge phase to one another. The shorting transistor () is arranged in or on the respective sense amplifier (SA) jointly for all bit line pairs () which can be connected to a repetitive sense amplifier (SA), and it can be switched by a separate shorting control signal (EQLx) via a dedicated control line ().

RAM store and control method therefor

The invention provides a method for testing a circuit unit () to be tested, in which a test time is reduced, at least one word line (N) of the circuit unit () to be tested being activated by application of at least one test signal () to the word line (N), the at least one word line (N) being deactivated by removal of the test signal () from the word line (N), the word lines among all the word lines (N) which have not run through an activation-deactivation cycle being read out in order to determine an influence of the activation and deactivation, and the test result being output.

Method for testing a circuit unit to be tested and test apparatus

An integrated memory can include a memory cell array, which has word lines for the selection of memory cells, bit lines for reading out or writing data signals of the memory cells, and a sense amplifier connected to bit lines of a bit line pair at one end of the bit line pair. In an activated state during a memory access, at least one activatable isolation circuit which is switched into one of the bit line pairs can isolate a part of the bit line pair, which is more remote from the sense amplifier from the sense amplifier. As a result, the effective capacitance of the bit lines can be significantly reduced during the memory access.

Integrated memory

An integrated semiconductor memory includes a DRAM memory, in which primary sense amplifiers (SA) are coupled to a bit line (BL) of a respective cell block and can be connected to a common local data line (LDQ) by means of a respective assigned CSL switch in response to a CSL signal and in which an MDQ/LDQ switch arrangement connects a main data line (MDQ) to the local data line (LDQ) of a respective cell block in response to an MDQ/LDQ switch signal. In the case of the semiconductor memory, a control input of each CSL switch is connected to an AND element, which ANDs the CSL signal with the MDQ/LDQ switch signal and thereby activates the CSL switches only in cell blocks in which a word line has been activated.

Integrated semiconductor memory circuit and a method for operating the same

A RAM memory with a shared sense amplifier structure, in which sense amplifiers are arranged in strips between two adjacent cell blocks and are configured as differential amplifiers. In an exemplary embodiment, a one of four bit line pairs of the two adjacent cell blocks can be selected for connection to a sense amplifier at any one time using respective isolation transistor pairs, in response to a connection control signal fed to the latter. A signal sent on a word line coupled to a memory cell associated with the selected bit line pair, provides access to the memory cell by the sense amplifier.

DRAM memory with a shared sense amplifier structure

An integrated semiconductor memory, and method for operating such a memory, in particular a DRAM memory, having local data lines (LDQT, LDQC) segmented in the column direction (Y), which local data lines can be connected by a CSL switch in response to a column select signal fed via a CSL line (CSL) running in the row direction (X) to primary sense amplifiers for transferring or accepting spread data signals to or from bit lines of the respective segment (I, II, III), LDQ switches are arranged at the interfaces between adjacent segments of the local data lines (LDQT, LDQC) for their connection to the local data lines (LDQT, LDQC) of adjacent segments (I, II, III). LDQ switches, depending on a control signal fed separately to each of said LDQ switches, are closed during a precharge phase, which takes place before each read cycle, of at least two adjacent LDQ segments.

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Dorfen, Germany

Manfred Proell