Freescale Semiconductor,inc.

Nxp Usa, Inc.

Manfred P Thanner

Michael Rohleder

Stephan G Mueller

Michael Andreas Staudenmaier

Juergen Frank

Stefan Singer

Gary Hay

Alistair Robertson

Carl Culshaw

Anthony M Reipold

Sunny Gupta

Florian Bogenberger

Christopher Temple

Alan Devine

Mathias Rausch

Alexandre Pierre Palus

Michael Johnston

Nancy H Amedeo

Thomas Wuerz

Gregor Pokorny

Leonard Link

In at least one embodiment of the disclosure, a method includes detecting an error in a local memory shared by redundant computing modules executing in delayed lockstep. The method includes pausing execution in the redundant computing modules and handling the error of the local memory. The method includes resuming execution in delayed lockstep of the redundant computing modules in response to the handling of the error.

Multi-channel network-on-a-chip

A system on chip, comprising a processing unit for executing processes, a memory unit, and a memory control unit connected between the processing unit and the memory unit, is described. The memory control unit allocates a memory region to a process. The memory control unit comprises a process activity counter which counts a duration of the process or transactions by the process to or from the memory region and which maintains a process activity count representing the counted duration of the process or the counted transactions to or from the memory region. The memory control unit disables the memory region in response to the process activity count exceeding a maximum process activity count. Notably, it blocks the memory region against further transactions by the process and against transactions by any other processes. A method of operating a system on chip is also described.

System on chip and method of executing a process in a system on chip

A memory controller is used to verify authenticity of data stored in a first memory unit, and includes a secure memory unit which stores a pre-stored value representative of the authenticity of the data to be written in the first memory unit. A processing system calculates a value representative of the data in the first memory unit after a write cycle. The calculation of the calculated value is triggered by the write cycle. The calculated value is compared with the pre-stored value to verify whether the data stored in the first memory unit after the write cycle has been altered in accordance with the authenticity. By comparing the calculated value with the pre-stored value, authenticity of the data stored in the first memory unit after the write cycle is verified, thus preventing the memory controller from operating if the data written to the first memory unit is not authentic.

Memory controller to verify authenticity of data

A system on chip having two or more responder units and two or more protection units is provided. Each of the responder units comprises a set of responder elements. Each of the protection units is associated with and protects one of the responder units and is arranged to provide a group mapping. The group mapping assigns one or more group identifiers to each of the responder elements of the respective responder unit.

System on chip

A communication apparatus for preventing the broadcasting of unauthorized messages on a broadcast bus network, the communication apparatus comprising:

Illegal message destroyer

A built-in self test system comprises an integrated circuit device comprising a plurality of functional units coupled to built-in self test circuitry; a low power control unit operable to switch the integrated circuit device into a low power mode and to generate a BIST wake-up signal during or before entering the low power mode; and a built-in self test control unit coupled to the built-in self test circuitry and the low power control unit and arranged to initiate a built-in self test when receiving the BIST wake-up signal.

Built-in self test system, system on a chip and method for controlling built-in self tests

A device securely accesses data in a memory via an addressing unit which provides a memory interface for interfacing to a memory, a core interface for interfacing to a core processor and a first and second security interface. The device includes a security processor HSM for performing at least one security operation on the data and a remapping unit MMAP. The remapping unit enables the security processor to be accessed by the core processor via the first security interface and to access the memory device via the second security interface according to a remapping structure for making accessible processed data based on memory data. The device provides a clear view on encrypted memory data without requiring system memory for storing the clear data.

Device having a security module

A data path configuration component for configuring at least one data path setting within a signal processing device is described. The data path configuration component is arranged to receive an indication of an operating mode of the signal processing device, and dynamically configure the at least one data path setting within the signal processing device based at least partially on the received indication of an operating mode of the signal processing device.

Data path configuration component, signal processing device and method therefor

A mode-controlled voltage excursion detector apparatus for monitoring a supply voltage of a power supply applied to a load and a method of operating thereof is described. A voltage monitor is configured to detect an excursion event if the supply voltage exceeds or falls below at least one defined threshold, to generate an excursion event signal upon detection of the excursion event and to provide the generated excursion event signal to the excursion event output for being outputted via an excursion event output. A sensitivity control module is configured to receive a signal indicative of potential voltage excursions. A sensitivity control module is further operatively coupled to the sensitivity control input and configured to disable the outputting of an excursion event signal generated during a defined period of time in response to the reception of the signal, which triggers the disabling of the outputting.

Mode-controlled voltage excursion detector apparatus and a method of operating thereof

An integrated circuit device comprising at least one memory interface module arranged to be operably coupled between at least one data storage device and a plurality of master devices within a data processing system. The at least one memory interface module comprises a plurality of buffers and at least one data access control module. The at least one data access control module being arranged to fetch data from the at least one data storage device in response to a received memory access request comprising a master device identifier, select at least one buffer based at least partly on the master device identifier of the received access request, and load the fetched data into the selected at least one buffer.

Integrated circuit device and method for providing data access control

In a system on chip responder units comprise one or more responder elements and is associated with one or more protection units. A request analysis unit is arranged to receive from a requesting requestor unit a request for access to one or more target responder elements among responder elements within a target responder unit among the responder units. The request analysis unit determines relevant protection data based on the request and an authorization list, which comprises one or more entries For each entry of the authorization list: taking access requirements specified by the respective entry into account if one or more of the target responder elements are part of the group of responder elements specified by the respective entry. The request analysis unit provides the relevant protection data to one or more target protection unit(s) associated with the responder unit(s), and located in a hierarchical path between the requesting requestor unit requestor unit and the target responder unit. The target protection unit(s) are arranged to perform a protective action for the target responder elements based on relevant protection data.

A system for distributing an available memory resource comprising at least two random access memory (RAM) elements and RAM routing logic. The RAM routing logic comprises configuration logic to dynamically distribute the available memory resource into a first memory area providing redundant memory storage and a second memory area providing non-redundant memory storage. The system may further comprise bus access ports which support at least one of concurrent access by a bus access port to access redundantly stored data or non-redundantly stored data, or concurrent access by at least two bus access ports to respective RAM elements to access redundantly stored data or to a respective one of the RAM elements to access non-redundantly stored data. Comparison logic and error detection or correction logic may be provided to detect or correct errors in information read from the RAM elements.

System for dynamically distributing an available memory resource to redundant and non-redundant storage areas using RAM routing logic

A system comprises one or more slave elements operably coupled to a plurality of master devices. A central protection function is operably coupled to a first communication bus and configured to control data flow between the one or more slave elements and the plurality of master devices via the communication bus.

Controlling the access of master elements to slave elements over a communication bus

A system comprises a first master element; and at least one shared communication element arranged to operably couple the first master element to at least one slave element. The system further comprises at least one validation element located on at least one further validation path located between the first master element and the at least one slave element, wherein the at least one validation element is arranged to validate at least one of: at least one access request by the first master element; and a response to an access request from the at least one slave element.

Processor based system having ECC based check and access validation information means

A system comprises at least two random access memory (RAM) elements arranged to store data redundantly. The system further comprises RAM routing logic comprising comparison logic operably coupled to the at least two RAM elements and arranged to compare redundant data read from the at least two RAM elements, and check and validation logic, independent of the RAM routing logic, operably coupled to the at least two RAM elements and arranged to additionally detect an error in the redundant data read from the at least two RAM elements and provide an error indication signal to the RAM routing logic in response thereto. The RAM routing logic further comprises selection logic arranged to dynamically select redundant data from one of the at least two RAM elements based on the comparison of the redundant data and the error indication signal.

Growing community of inventors

Neubiberg, Germany

Manfred P Thanner