Infineon Technologies Ag

Manfred Moser

Erwin Thalmann

Martin Versen

Thomas Huber

Frank Adler

Daniel Mysliwitz

Achim Schramm

Andreas Doll

Richard Antretter

The invention provides a device for monitoring electronic circuit units during an initialization phase. The device has at least one internal data line () for forwarding internal data () in the electronic circuit unit () and at least one data connection line () for outputting the internal data from the electronic circuit unit () and for inputting external data () into the electronic circuit unit (). A changeover unit (), which is intended to change over the data connection line () either to the internal data line () or to internal signal lines (), and a combinational logic unit () for combining an initialization signal (), which is provided by the electronic circuit unit () to be monitored, with an external changeover signal (), which is supplied via a changeover signal input () of the electronic circuit unit () to be monitored, are also provided. An activation signal (), which is output by the changeover unit (), is used to change over the data connection line to the internal signal lines () when the initialization signal () indicates an initialization mode of the electronic circuit unit ().

Monitoring device for monitoring internal signals during initialization of an electronic circuit

An electronic memory device for storing data comprises a memory cell array arranged in at least one memory bank and comprising memory cells in which information is stored. The electronic memory device further comprises word lines and bit lines for addressing and reading the memory cells of the memory cell array. The word lines are configured to refresh in a refresh mode the information stored in the memory cells of the memory cell area by applying a predetermined activation potential at a predetermined refresh rate to the word lines. All word lines of the memory bank which do not have a common bit line are activated simultaneously in the refresh mode.

Method for activating a plurality of word lines in a refresh cycle, and electronic memory device

The invention provides a test apparatus for testing a circuit unit () to be tested having a test system (), a control bus () for transferring control data (), an address bus () for transferring addressing data () and a data bus () for exchanging test data () between the test system () and the circuit unit () to be tested. A voltage generating device () connected between the test system () and the circuit unit () to be tested serves for generating a predeterminable operating voltage output signal (-) for the voltage supply of the circuit unit () to be tested in a manner dependent on a control signal () that is provided by the test system () and fed via the control bus ().

Test apparatus and method for testing circuit units to be tested

Two methods check functional capability of electrical connections between address lines of a printed circuit board of a memory module and address line contacts of an integrated semiconductor memory chip mounted on the printed circuit board. Ruptured solder contacts are conventionally examined optically or investigated by electrical resistance measurements; however, the latter do not work in the case of memory modules with a number of semiconductor chips, the pin contacts of which are connected in parallel by the address lines. The methods make it possible to locate interrupted contacts on individual address lines by the indirect use of a write-read access to the semiconductor memory chip, specifically utilizing the misrouting of writing and reading commands produced by defective contact connections.

Method of checking electrical connections between a memory module and a semiconductor memory chip

A method and an apparatus for testing an SDRAM are described. The SDRAM is used as a main memory in the PC, and an additional circuit configuration is accommodated on a plug-in board and has an additional memory in the form of an SRAM and logic circuits. The method according to the invention allows the SDRAM to be tested in a module bank in the running PC to be set deliberately to a test mode. In this case the code for test mode activation is modified by a high-level language program (PASCAL) in accordance with the user requirements, is copied to the additional memory on the plug-in board, and is then called by the high-level language program using MS DOS. After activation of the selected test mode by a code programmed in Assembler, a defined jump is made back to the calling program once again. This allows the use of the test mode provided in the SDRAM in standard PCs and using standard operating systems. This greatly increases the test options for SDRAMs on standard PCs.

Method and apparatus for testing an SDRAM memory used as the main memory in a personal computer

Signal transit times on printed circuit boards which are equipped with all the passive components but without any active components can be determined using automatic standard test equipment composed of a standard test unit and a performance board with fittings attached thereto. In that first, using a standard routine of the test unit, a transit time is measured on the performance board from the CIF connector as far as the fitting, then a printed circuit board is plugged into the fitting location determined for it and then the sum transit time of the CIF connector is measured as far as the landing pad on the printed circuit board. By forming differences between the two measured values, the transit times on a printed circuit board can be measured with a high degree of precision with the automatic standard test equipment used in standard module testing technology.

Growing community of inventors

Dachau, Germany

Manfred Moser