Siemens Aktiengesellschaft

Infineon Technologies Ag

Infineon Technologies LLC

Manfred Mauthe

Henrik Icking

Kurt Hoffmann

Rudolf Koch

Hans-Jorg Pfleiderer

Jens Sauerbrey

Heiner Klar

Various aspects are described, such as a method for operating a level shifter, in which the level shifter is coupled to a first supply voltage and a second supply voltage different from the first supply voltage. The method may include detecting whether the first supply voltage is present, and decoupling an input of the level shifter from an output of the level shifter responsive to detecting that the first supply voltage is not present.

Level shifting

In order to generate a control signal for adjusting a driver stage with an adjustable output impedance, an impedance signal is generated for a measure of the output impedance of the driver stage. The difference between the impedance signal and a reference signal is calculated, and passed to a sigma-delta modulator to generate a digital bitstream signal. The control signal is then generated depending on the bitstream signal, where the frequencies of the two signal states in the bitstream signal are evaluated by means of digital counters. Depending on the difference of the determined frequencies of the two signal states, a counter is increased or reduced, and the control signal is generated depending on the count of the counter. The impedance signal may be generated by a replica circuit of a pull-up region or a pull-down region of the driver stage to be adjusted.

Adjusting driver stage output impedance

To output a digital signal in particular according to the LVDS (low voltage differential signalling) standard, a driver stage is supplied with a constant current and thus supplies the digital signal in the form of a current signal with defined current values. As a result of line capacitances of a transmission line, because of the current limited according to the standard the edge steepness and hence the maximum transmittable bit rate can deteriorate. According to the invention, therefore, at least essentially in synchronization with a triggering of the driver stage, at least one current increase signal is generated which via a capacitor causes an additional current increase in the output current of the driver stage. Preferably, the current increase signal via the respective capacitor is switched directly to an output of the driver stage. By using a capacitor, with very little expenditure a limited current pulse can be switched in a temporally targeted manner on the switching processes of the driver stage.

Process and device for outputting a digital signal

The invention specifies a circuit arrangement for voltage regulation in which, in addition to a control loop having a comparator (), an output stage () and a feedback path, an auxiliary regulator () is provided which limits the voltage drop across the output stage () and, for this purpose, comprises a control element () and a further comparator (). Hence, the output stage () of the voltage regulator may advantageously have a withstand voltage which is lower than the supply voltage which can be supplied at the input (). On account of its good supply voltage suppression, the voltage regulator described is particularly well suited to supplying on-chip VCOs.

Circuit arrangement for voltage regulation

A digital-analog converter having high linearity is based on two sigma-delta modulators of second order which are fed back in a cascaded fashion and via differentiators. The first modulator has a quantizer with only three stages, an output signal of which delivers an analog output signal via a three-stage digital-analog converter and a low-pass filter. The particularly high linearity, the good stability and the relatively large bandwidth with reference to clock frequency are advantages of the digital-analog converter.

Device for digital-analog conversion with high linearity

A sigma-delta modulator includes a first integrator receiving a difference between an input signal being weighted by a first coefficient, and a first reference signal being weighted by a second coefficient. A second integrator receives a difference between the output signal of the first integrator being weighted by a third coefficient, and the first reference signal being weighted by a fourth coefficient. A first quantizer receives the output signal of the second integrator being weighted by a fifth coefficient. A first digital/analog converter converts the output signal of the first quantizer into the first reference signal. A third integrator receives a difference between the output signal of the second integrator being weighted by a sixth coefficient, and a second reference signal being weighted by a seventh coefficient. A second quantizer receive the output signal of the third integrator being weighted by an eighth coefficient. A logic circuit adds together the output signals of the first and second quantizers. A second digital/analog converter converts the output signal of the logic circuit into the second reference signal. A first digital filter is connected downstream of the first quantizer, a second digital filter is connected downstream of the second quantizer, and the digital filters supply output signals being added together.

Sigma-delta modulator

An integrated compression amplifier that can be constructed in CMOS technology and whose threshold voltages are programmable. The compression amplifiers can be built into a multi-channel AGC device, so that the circuit can be co-integrated on a 'switched capacitor' filter chip in CMOS technology. The compression amplifier circuit essentially involve a feedback amplifier whose gain is controlled by the output amplitude. To this end, an amplifier SC having variable gain constructed as a 'switched capacitor' amplifier, a rectifier unit GR' as well as a low-pass filtr TP' are in a feedback branch and a two quadrant multiplier ZM1 is connected between the input and output Ue', Ua' of the compression amplifier. The output of the lo-pass filter TP' is thereby fed back onto the control input of the two quadrant multiplier ZM'.

Integrated compression amplifier having programmable threshold voltage

integrated voltage multiplier circuit for low supply voltage. In order to improve the signal-to-noise ratio in battery-operated switched capacitor filter circuits in hearing aids, the range of modulation can be increased by doubling the supply voltage. A circuit for voltage multiplication in CMOS technology generates a negative voltage for a given voltage. In order to be able to utilize both clock phases, a two-stage embodiment is selected, both of these working onto a smoothing capacitor. The voltage multiplier circuit is driven by a fourth inverter stage and with a level converter having a connected, third inverter stage.

Integrated voltage multiplier circuit for low supply voltage

A circuit for voltage multiplication has a capacitor which is connectible via first switching transistors to a supply voltage source and via further first switching transistors in series with the supply voltage source and with a storage capacitor which is connected in parallel to the circuit output. Clock voltages for driving the first switching transistors are switchable in amplitude from a value corresponding to the supply voltage to the value corresponding to the output voltage. In order to achieve high efficiency of the circuit, a clock voltage generator is controllable for amplitude switch over via a supply line which is connectible via a second switching transistor to the supply voltage source and is connectible via a third switching transistor to the circuit output, whereby these switching transistors are driven via the outputs of the comparator which compares the supply voltage to the output voltage. The circuit may advantageously be employed in hearing aid circuits.

Circuit for voltage multiplication

A charge coupled device (CCD) input circuit operates according to the fill and spill principle. An arrangement of a distributor electrode and a barrier electrode, and a drain diode laterally adjacent the electrode row, provide for the separation and removal of an undesirable d.c. component from the a.c. component of the signal. The optimum working point, in contrast with known CCD input circuits, lies at full modulation. The invention provides the system having a high degree of linearity with a high amplification.

Charge coupled device (CCD) input circuit operating according to the

An integrated rectifier circuit has a doped semiconductor body having first and second oppositely doped regions therein and is covered by an electrically insulating layer on which a first pair of input gate electrodes are disposed which are associated with the first oppositely doped region and on which a second pair of input gate electrodes are disposed associated with the second oppositely doped region. The oppositely doped regions are connected to a clock pulse voltage and all of the input gate electrodes are connected to a constant voltage having a magnitude such that a uniform surface potential exists in the semiconductor regions covered by the electrodes. The input gate electrode of the first pair which is disposed at a greater distance from the first oppositely doped region and the input gate electrode of the second pair which is disposed closer to the second oppositely doped region are charged with the alternating voltage component of an input signal. A charge transfer device transfer channel covered with transfer electrodes is connected to the semiconductor regions covered by the input electrodes and a charge transfer device output stage couples an output signal to external circuitry in which the alternating voltage component is rectified.

Integrated rectifier circuit

A digital CCD arrangement is provided in which an output signal is emitted which is regenerated with respect to its voltage range, and is substantially insensitive to adverse influences. In this arrangement, the last shift electrode preceding the output end zone is coupled with respect to potential to a circuit point of a transistor stage, which point in the event of a quantity of charge carriers representing logic level '1,' the output end zone experiences a change in potential which corresponds to the change in potential beneath the other shift electrodes. Between the last preceding shift electrode and the output end zone, there is arranged a further electrode which is insulated from the semiconductor layer and is connected to a second reference potential which corresponds to an intermediate value which is swept over by the potential across the circuit point.

Digital CCD arrangement

A storage element comprises a storage capacitor which has a storage electrode, arranged insulated over a doped semiconductor layer, connected to a constant voltage, and a selection element which manifest a gate connected to a word line, arranged in an insulated manner above the semiconductor layer. A source zone connected to a bit line is oppositely doped and arranged at the surface of the semiconductor layer. The selection element selectively connects the source zone to a surface storage region of the semiconductor layer which is disposed beneath the storage electrode. Between the storage electrode and the semiconductor layer an insulated electrode is provided and the semiconductor layer is additionally p-doped and n-doped in a zone beneath a portion, adjacent the selection element, of the electrode and an overflow electrode and an oppositely doped drain zone are provided on the side of the electrode opposite the selection element.

Dynamic storage element having static storage element behavior

A method and apparatus is disclosed for a fast switching digital differential amplifier system useful in regenerating information signals in charge coupled devices. The amplifier system has a first capacitance at an input point which is charged and discharged in accordance with a binary '0' or binary '1' at the input. A second capacitance and an output capacitance is provided with a predetermined charge thereon. In the event of a binary '1', the predetermined charge on the second and output capacitance is retained while the first capacitance is discharged. In the event of a binary '0', the second and output capacitances are discharged via a current sink. A flip-flop is connected to the output capacitance for accelerating the discharge of the same. Switching transistors are additionally provided for activating the flip-flop to achieve the desired fast-switching.

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Grosshelfendorf, Germany

Manfred Mauthe