Infineon Technologies Ag

Manfred Kotek

Franz Hirler

Joost Larik

Walter Rieger

Hans-Joachim Schulze

Johannes Baumgartl

Ralf Otremba

Martin Poelzl

Oliver Haeberlen

Oliver Häberlen

Thomas Christian Neidhart

Josef Maerz

Martin Pölzl

Christian Krenn

Markus Harfmann

Nikolaus Bott

Markus Zundel

Frank Dieter Pfirsch

Manfred Engelhardt

Adolf Koller

Ralf Henninger

Werner Kroeninger

Abdul Rahman Mohamed

A semiconductor device includes a semiconductor substrate, a doped zone, a polysilicon layer and an elongate plug structure. The doped zone is within the semiconductor substrate. The polysilicon layer is disposed in a trench electrically isolated from the semiconductor substrate by an insulating layer. The elongate plug structure extends in a lateral direction in or above the semiconductor substrate. The elongate plug structure provides electrical connection between the doped zone and the polysilicon layer.

Semiconductor device

A semiconductor arrangement is produced by providing a semiconductor carrier of a second conduction type and epitaxially growing a first semiconductor zone of a first conduction type on the carrier. The first semiconductor zone includes a semiconductor base material doped with first and second dopants which are made of different substances which are both different from the semiconductor base material. The first dopant is electrically active and causes a doping of the first conduction type in the semiconductor base material, and causes a decrease or an increase of a lattice constant of the first semiconductor zone. The second dopant causes one or both of hardening of the first semiconductor zone and an increase of the lattice constant of the first semiconductor zone if the first dopant causes a decrease, or a decrease of the lattice constant of the first semiconductor zone if the first dopant causes an increase.

Method of producing a semiconductor arrangement

In one embodiment, the semiconductor die includes a selective epitaxial layer including device regions, and a masking structure disposed around sidewalls of the epitaxial layer. The masking structure is part of an exposed surface of the semiconductor die.

Singulation through a masking structure surrounding expitaxial regions

A first semiconductor zone of a first conduction type is formed from a semiconductor base material doped with first and second dopants. The first and second dopants are different substances and also different from the semiconductor base material. The first dopant is electrically active and causes a doping of the first conduction type in the semiconductor base material, and causes either a decrease or an increase of a lattice constant of the pure, undoped first semiconductor zone. The second dopant may be electrically active, and may be of the same doping type as the first dopant, causes one or both of: a hardening of the first semiconductor zone; an increase of the lattice constant of the pure, undoped first semiconductor zone if the first dopant causes a decrease, and a decrease of the lattice constant of the pure, undoped first semiconductor zone if the first dopant causes an increase, respectively.

Semiconductor arrangement

A semiconductor device has elongate plug structures extending in the lateral direction. The plug structures serve as electrical lines in order to enable locally defined lateral current flows within the cell array, within edge regions or logic regions of the semiconductor device.

A method of fabricating a semiconductor chip includes the providing an adhesive layer on the outer area of the active surface of a device wafer and attaching a rigid body to the active surface by the adhesive layer. The device wafer is thinned by treating the passive surface of the device wafer. A first backing tape is connected to the passive surface of the device wafer. The outer portion of the rigid body is separated from the central portion of the rigid body and the outer portion of the device wafer is separated from the central portion of the device wafer. The central portion of the rigid body, the outer portion of the device wafer and the outer portion of the rigid body are removed from the first backing tape. The device wafer may be diced into semiconductor chips.

Method of producing a thin semiconductor chip

The invention relates to a vertical arrangement of at least two semiconductor components which are electrically insulated from one another by at least one passivation layer. The invention likewise relates to a method for fabricating such a semiconductor arrangement. A semiconductor arrangement is specified in which, inter alia, the risk of cracking at the metallization edges, for example, caused by thermomechanical loading, is reduced and the fabrication-dictated high content of radical hydrogen is minimized. Furthermore, a method for fabricating such a semiconductor arrangement is specified.

In the case of the cost-effective method according to the invention for fabricating a power transistor arrangement, a trench power transistor arrangement () is fabricated with four patterning planes each containing a lithography step. The power transistor arrangement according to the invention has a cell array () with cell array trenches () each containing a field electrode structure () and a gate electrode structure (). The field electrode structure () is electrically conductively connected to the source metallization () by a connection trench () in the cell array ().

Power transistor arrangement and method for fabricating it

When fabricating trench power transistor arrangements () with active cell array trenches () and passive connecting trenches (), the cell array trenches () are provided in greater width than the connecting trenches (). An auxiliary layer () is deposited conformally onto a lower field electrode structure () in the cell array trenches () and the connecting trenches () and is etched back as far as the top edge in the connecting trenches (), which removes it from the cell array trenches (). The auxiliary layer () allows the gate oxide () to be patterned without a complex mask process. An edge trench (), with an electrode, on the potential of the field electrode structure () shields the cell array () from a drain potential.

A trench power semiconductor component is described which has an edge cell in which an edge trench is provided. The edge trench, at least on an outer side wall, has a thicker insulating layer than an insulating layer of trenches of the cell array. This simple configuration provides a high dielectric strength and is economical to produce.

Trench power semiconductor

A trench MOS-transistor includes a body region strengthened by an implantation area that faces the drain region to increase the avalanche resistance.

Trench MOS transistor

A method for fabricating a trench MOS transistor includes the step of at least partly filling the trench with a conductive material which is isolated from the inner surface of the trench by an insulating layer. The insulating layer has a layer thickness that is larger in the region of the lower end of the trench than at the upper end of the trench.

Growing community of inventors

Villach, Austria

Manfred Kotek