Globalfoundries Inc.

Infineon Technologies Ag

Samsung Electronics Co., Ltd.

International Business Machines Corporation

Manfred Eller

Hui Zang

Min-Hwa Chi

Richard Lindsay

Srikanth Balaji Samavedam

Henning Haffner

Jin-Ping Han

Brian Joseph Greene

Richard J Carter

Manoj Joshi

Xusheng Kevin Wu

Yi Qi

Jiang Yan

Laegu Kang

Michael Ganz

Puneet Khanna

Sri Charan Vemula

Vara G Reddy Vakada

Zhijiong Luo

Chun-Yung Sung

Yanxiang Liu

Jin Ping Liu

Rohit Pal

Kwan-Yong Lim

Alois Gutmann

Matthias Hierlemann

Ja-Hum Ku

Roland Hampp

Johannes M Van Meer

Bongki Lee

Min-chul Sun

Srikanth Balaji Samavedan

Jerome J B Ciavatti

Thomas Schiml

Haiting Wang

Hong Yu

Shesh Mani Pandey

Victor Chan

Jun Yuan

Sunfei Fang

Cornelius Christian Russ

Nam Sung Kim

Haoren Zhuang

Seunghwan Lee

Daniel J Jaeger

Yong Meng Lee

Bingwu Liu

Jingyu Lian

Roman Knoefler

Matthias Lipinski

David Alvarez

Changyong Xiao

Xiaodong Yang

Narasimhulu Kanike

Lun Zhao

Wanxun He

Seong Yeol Mun

Jie Chen

Johannes Marinus Van Meer

Konstantin G Korablev

Choongryul Ryou

Wee Lang Tan

A vertical SRAM cell includes a first (1) inverter having a 1common gate structure operatively connecting channels of a 1pull-up (PU) and a 1pull-down (PD) transistor. A 1metal contact electrically connects bottom source/drain (S/D) regions of the 1PU and 1PD transistors. A second (2) inverter has a 2common gate structure operatively connecting channels of a 2PU and a 2PD transistor. A 2metal contact electrically connects bottom S/D regions of the 2PU and 2PD transistors. A 1cross-coupled contact electrically connects the 2common gate structure to the 1metal contact. The 2common gate structure entirely surrounds a perimeter of the 1cross-coupled contact. A 2cross-coupled contact electrically connects the 1common gate structure to the 2metal contact. The 1common gate structure entirely surrounds a perimeter of the 2cross-coupled contact.

Method of manufacturing a vertical SRAM with cross-coupled contacts penetrating through common gate structures

A device includes a substrate having an N-active region and a P-active region, a layer of silicon-carbon positioned on an upper surface of the N-active region, a first layer of a first semiconductor material positioned on the layer of silicon-carbon, a second layer of the first semiconductor material positioned on an upper surface of the P-active region, and a layer of a second semiconductor material positioned on the second layer of the first semiconductor material. An N-type transistor is positioned in and above the N-active region and a P-type transistor is positioned in and above the P-active region.

Transistor device structures with retrograde wells in CMOS applications

A semiconductor memory device includes, for example, a substrate having a fin having a web portion extending from the substrate and a first overhanging fin portion extending outward from the web portion and spaced from the substrate, the fin comprising a source/drain region in the web portion of the fin, a first source/drain region in the first overhanging fin portion, an isolation material surrounding the web portion and disposed under the first overhanging fin portion of the fin, an upper surface of the isolation material being below an upper surface of the fin, a first gate disposed over the fin between the source/drain region in the web portion of the fin and the first source/drain region in the first overhanging fin portion of the fin, and a capacitor operably electrically connected to the first source/drain region in the first overhanging fin portion.

Semiconductor memory devices having an undercut source/drain region

Circuit structures, such as inverters and static random access memories, and fabrication methods thereof are presented. The circuit structures include, for instance: a first transistor, the first transistor having a first channel region disposed above an isolation region; and a second transistor, the second transistor having a second channel region, the second channel region being laterally adjacent to the first channel region of the first transistor and vertically spaced apart therefrom by the isolation region thereof. In one embodiment, the first channel region and the isolation region of the first transistor are disposed above a substrate, and the substrate includes the second channel region of the second transistor.

Circuit structures with vertically spaced transistors and fabrication methods

One illustrative method disclosed herein includes, among other things, forming first and second adjacent gates above a semiconductor substrate, each of the gates comprising a gate structure and a gate cap, forming a conductive resistor structure between the first and second adjacent gates, the conductive resistor structure having an uppermost surface that is positioned at a level that is below a level of an uppermost surface of the gate caps of the first and second adjacent gates, and forming first and second separate conductive resistor contact structures, each of which is conductively coupled to the conductive resistor structure.

Methods of forming a resistor structure between adjacent transistor gates on an integrated circuit product and the resulting devices

A method of reducing parasitic capacitance includes providing a starting semiconductor structure, the starting semiconductor structure including a semiconductor substrate with fin(s) thereon, the fin(s) having at least two dummy transistors integrated therewith and separated by a dielectric region, the dummy transistors including dummy gates with spacers and gate caps, the fin(s) having ends tucked by the dummy gates. The method further includes removing the dummy gates and gate caps, resulting in gate trenches, protecting area(s) of the structure during fabrication process(es) where source/drain parasitic capacitance may occur, and forming air-gaps at a bottom portion of unprotected gate trenches to reduce parasitic capacitance. The resulting semiconductor structure includes a semiconductor substrate with fin(s) thereon, FinFET(s) integral with the fin(s), the FinFET(s) including a gate electrode, a gate liner lining the gate electrode, and air-gap(s) in gate trench(es) of the FinFET(s), reducing parasitic capacitance by at least about 75 percent as compared to no air-gaps.

Source/drain parasitic capacitance reduction in FinFET-based semiconductor structure having tucked fins

Circuit structures, such as inverters and static random access memories, and fabrication methods thereof are presented. The circuit structures include, for instance: a first transistor, the first transistor having a first channel region disposed above an isolation region; and a second transistor, the second transistor having a second channel region, the second channel region being laterally adjacent to the first channel region of the first transistor and vertically spaced apart therefrom by the isolation region thereof. In one embodiment, the first channel region and the isolation region of the first transistor are disposed above a substrate, and the substrate includes the second channel region of the second transistor. In another embodiment, the first transistor includes a fin structure extending from the substrate, and an upper portion of the fin structure includes the first channel region and a lower portion of the fin structure includes the isolation region.

FINFET circuit structures with vertically spaced transistors and fabrication methods

One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a gate structure between a pair of gate spacers within a dielectric layer and substantially surrounding a fin, wherein the gate structure is disposed adjacent to a channel region within the fin; and a source/drain contact extending within the dielectric layer to a source/drain region within a fin, the source/drain contact being separated from the gate structure by at least one gate spacer in the pair of gate spacers, wherein the channel region and the source/drain region provide electrical connection between the gate structure and the source/drain contact.

Integrated circuit structure without gate contact and method of forming same

Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.

Integrated circuits and methods of design and manufacture thereof

Vertical SRAM structure with cross-coupling contacts penetrating through common gates to bottom S/D metal contacts

Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming a gate dielectric over the semiconductor wafer, and forming a gate over the gate dielectric. At least one recess is formed in the semiconductor wafer proximate the gate and the gate dielectric, at least a portion of the at least one recess extending beneath the gate. The at least one recess in the semiconductor wafer is filled with a semiconductive material.

Semiconductor devices and methods of manufacture thereof

One illustrative method disclosed herein includes performing a first plurality of epitaxial deposition processes to form a first plurality of semiconductor materials selectively above the N-active region while masking the P-active region, performing a second plurality of epitaxial deposition processes to form a second plurality of semiconductor materials selectively above the P-active region while masking the N-active region, forming an N-type transistor in and above the N-active region and forming a P-type transistor in and above the P-active region.

Methods of forming transistors with retrograde wells in CMOS applications and the resulting device structures

Growing community of inventors

Beacon, NY, United States of America

Manfred Eller