Lucent Technologies Inc.

Cirrus Logic Inc.

Agere Systems Inc.

Vitesse Semiconductor Corporation

Cicada Semiconductor Corporation

Agere Systems Guardian Corp.

Mandeep Singh Chadha

Shawn R McCaslin

Nicholas R Van Bavel

Prabir C Maulik

Mile Milisavljevic

Marty Lynn Pflum

James David Barnette

Zhuo Fu

James A McIntosh

Shawn Robert Mccaslin

A method switches master/slave timing in a communication network without traffic disruption. The method includes a master device informing a slave of timing loss. The master device additionally begins transmitting with timing from a local reference clock and begins receive timing recovery. The slave freezes its receive timing recovery and locks its transmit clock. The master device transitions its transmit timing to use the recovered receive clock. The slave gradually switches to transmitting using its local clock signal. The method may be used in synchronous Ethernet networks.

Method for switching master/slave timing in a 1000BASE-T link without traffic disruption

An echo canceling system, method of attenuating echo, and a bit pump and transceiver employing the system and method. The echo canceling system is couplable between a transmit and receive path of the bit pump and receives and attenuates the echo in a receive signal propagating along the receive path. In one embodiment, the echo canceling system includes a slave echo canceling stage that employs a filter coefficient to attenuate the echo. The echo canceling system also includes a separation circuit, coupled to the slave echo canceling stage, that generates data representing a residual echo substantially exclusive of the receive signal. The echo canceling system still further includes a master echo canceling stage, coupled to the separation circuit, that receives the data and modifies the filter coefficient based thereon.

Echo canceling system for a bit pump and method of operating the same

A separation circuit, method of determining a residual level of an echo, and an echo canceling system, bit pump and transceiver employing the circuit and method. The echo canceling system employing the separation circuit is couplable between a transmit and receive path of the bit pump and generates an echo canceling signal. In one embodiment, the separation circuit includes a symbol determination circuit that accepts a receive signal, propagating along the receive path, substantially free of an echo and determines a symbol associated with the receive signal. The separation circuit also includes an estimator stage, coupled to the symbol determination circuit, that receives the symbol and provides an estimated receive signal. The separation circuit generates data representing a residual level of the echo as a function of the estimated receive signal and the echo canceling signal.

Separation circuit for an echo canceling system and method of operating the same

A filter circuit, method of configuring the filter circuit, and a bit pump and transceiver employing the circuit and method. In one embodiment, the filter circuit includes a noise prediction equalizer that generates a noise prediction equalizer coefficient during activation of the bit pump to reduce an intersymbol interference associated with a receive signal propagating along a receive path of the bit pump. The filter circuit also includes a decision feedback equalizer that generates a decision feedback equalizer coefficient during the activation of the bit pump to reduce the intersymbol interference associated with the receive signal. The noise prediction equalizer is concatenated with the decision feedback equalizer during showtime of the bit pump to form a precoder associated with a transmit path of the bit pump.

Filter circuit for a bit pump and method of configuring the same

Reduced GMII with internal timing compensation A data interface between first and second integrated circuits. An internal clock signal is generated internal to the first integrated circuit and operates in a first frequency. A data generator is provided for generating data from at least one edge of the internal clock for transmission to the second integrated circuit. a first delay block internal to the first integrated circuit delays the internal clock for a predetermined duration of time less than one-half clock cycle of said internal clock to provide a first delayed clock. The second integrated circuit is then operable to receive the transmitted first delayed clock and utilize the transmitted first delayed clock to sample the received data generated by the data generator.

Reduced GMII with internal timing compensation

A technique for performing gain calibration on an analog-to-digital converter (ADC) in which offset errors are canceled during gain calibration. In an ADC having a differential integrator at the input of a modulator, two calibration measurements are obtained at the output, one based on a calibration input and the second based on the reversal of the input polarity. The two measured outputs are subtracted from each other so that offset errors introduced by the converter during gain calibration are cancelled.

Accurate gain calibration of analog to digital converters

A technique for separating an operation of a digital stage into separate noise generation periods in order to time the generation of noise from the digital stage. The invention is utilized in a mixed-signal integrated circuit having analog and digital signals in which the timing of the noise generation ensures that noise is abated during an analog sampling event.

Growing community of inventors

Austin, TX, United States of America

Mandeep Singh Chadha