Vlsi Technology, Inc.

Mandalagiri Chandrasekhar

Arnold Ginetti

Mossaddeq Mahmood

Balmukund K Sharma

A method and apparatus for characterizing the timing behavior of datapath in integrated circuit design and fabrication. A set of circuit specifications for an integrated circuit are developed and described in a hardware description language (HDL) description. A datapath library including datapath cells and a gate library including primitive gate cells are provided, and a netlist is synthesized from the HDL description. The netlist is composed of datapath cells from the datapath library and primitive gate cells from the gate library. If a datapath cell instance in the netlist does not meet the timing constraints imposed by a user for the circuit, an alternative datapath cell instance can be substituted for that cell instance in a resynthesis and optimization step. An integrated circuit is preferably fabricated as specified by the resynthesized netlist. The netlist is preferably resynthesized multiple times in an iterative loop to optimize the netlist according to the constraints. The timing information for alternative cells used in the resynthesis of the netlist can be retrieved from a timing database in one embodiment. Timing information for datapath cells is stored in the timing database in a pre-characterization process, and the location of the timing information in the timing database is stored in a query database. In another embodiment, timing information for alternative datapath cells is calculated dynamically during the resynthesis process for optimizing the timing of a netlist.

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Cupertino, CA, United States of America

Mandalagiri Chandrasekhar