Texas Instruments Corporation

Manar Ibrahim El-Chammas

Xiaopeng Li

Shigenobu Kimura

Himanshu Aggrawal

Jesse Coulon

A track and hold circuit includes a primary sampling capacitor, a primary switching transistor, and a cancellation transistor. The primary switching transistor is configured to provide a track state that connects an input signal to the primary sampling capacitor and a hold state that isolates the input signal from the primary sampling capacitor. The cancellation transistor is coupled to the primary sampling capacitor. The cancellation transistor is configured to inject a charge onto the primary sampling capacitor that cancels a charge injected onto the primary sampling capacitor by the primary switching transistor while the primary switching transistor is in the hold state.

Track and hold with active charge cancellation

An analog-to-digital converter (ADC) may include a comparator and a metastability detector. The comparator may be configured to compare an input signal to a reference signal to determine whether the input signal exceeds the reference signal. The comparator may also be configured to output a comparator output based on the determination. An ADC output may be based at least in part on the comparator output. The metastability detector may be coupled to the comparator and may be configured to determine, based at least in part on the comparator output, that the comparator is operating under metastable conditions and may output a metastability detector output.

Analog to digital converter error rate reduction

A system and method where a comparator is operatively coupled to an output of a Digital-to-analog Converter (DAC). The DAC may comprise a single DAC core or a plurality of interleaved DAC cores. The comparator is configured to capture properties of DAC core output. A digital engine is operatively coupled to receive output of the comparator and configured to calculate a cross-correlation between comparator output and input to the DAC core(s). The digital engine may be configured to determine if the skew of each DAC core is positive or negative and to determine if a skew correction term for the DAC core(s) should be decreased or increased, based on the skew of each DAC core being positive or negative, respectively. In interleaved DAC core devices, clock frequency sampling edges of the comparator may alternate between clock edges of each of the interleaved DAC cores.

Background calibration for digital-to-analog converters

A switched current pipeline analog-to-digital converter (ADC) integrated circuit. The integrated circuit comprises a track and hold circuit (T/H) and a residue amplifier. The T/H is configured to generate a differential output of the T/H based on an analog input. The residue amplifier is coupled to the T/H, configured to capture a sample of a common mode signal of the differential output of the T/H during a periodic pulse interval, wherein the pulse interval is less than half of the time duration of the period of the pulse, configured to generate a corrected input common mode feedback signal based in part on the sample of the common mode signal of the differential output of the T/H, and configured to generate a differential output of the residue amplifier based on the differential output of the T/H and based on the corrected input common mode feedback signal.

Common mode sampling mechanism for residue amplifier in switched current pipeline analog-to-digital converters

A circuit includes a track and hold (T/H) block to track an analog input signal during a track phase and to hold the analog input signal during a hold phase. A pipelined converter stage includes an analog to digital converter (ADC) receives the analog input signal from the T/H block and generates a digital output signal corresponding to the analog input signal. A digital to analog converter (DAC) element in the pipelined converter stage receives the digital output signal from the ADC and generates a current output signal representing an analog value for a portion of the analog input signal. A detector monitors the current output signal of the DAC element with respect to a predetermined reference current during the track phase and generates a trim signal if the current output signal is different from the predetermined reference current.

Background DAC calibration for pipeline ADC

A comparator circuit (FIG.) is disclosed. The circuit includes an amplifier circuit () arranged to produce an output signal (Vom,Vop). A first current source () is arranged to produce a first current through the amplifier circuit. A detector circuit () is arranged to produce a control signal () in response to a level of the output signal. A second current source () is arranged to produce a second current through the amplifier circuit in response to the control signal.

High speed dynamic comparator

An apparatus comprises: a coarse voltage level comparator that generates a coarse voltage level comparison; a folder, a fine analog to digital (ADC) comparator coupled to an output of the folder, wherein an output of the fine ADC is cyclical; an up encoder coupled to an output of the fine ADC encoder, the up encoder configured to output a first value if the cyclical output of the fine ADC is in a defined downward transition; and a fold information generator coupled to an output of the up encoder, wherein the fold information generator is configured to generate a determination as to in which fold an analog voltage occurs.

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Dallas, TX, United States of America

Manar Ibrahim El-Chammas