Kabushiki Kaisha Toshiba

Manami Kudou

Masaru Koyanagi

Toshiki Hisada

Katsuki Matsudera

Kazuhide Yoneya

A semiconductor device includes a semiconductor chip and a circuit formed in the semiconductor chip. Pads are arranged in a plurality of rows on the semiconductor chip and electrically connected to the circuit. The pads on adjacent rows are offset from each other. Leads are provided on the semiconductor chip and bonding wires selectively connect the leads to the pads.

Pad layout and lead layout in semiconductor device having a center circuit

A semiconductor memory device comprises a memory cell array, a first latch circuit group, and a second latch circuit group. The first latch circuit group sequentially outputs n/2 bit read data of n-bit read data from the memory cell array in response to sequentially shifted read control signals. The second latch circuit group sequentially outputs the remaining n/2 bit read data in response to the sequentially shifted read control signal.

Growing community of inventors

Tokyo, Japan

Manami Kudou