Fujitsu Corporation

Manabu Yamazaki

Kazuhiko Hatae

Tomoki Katou

Nobukazu Koizumi

Masato Oota

Masashi Sato

Hisao Nakashima

Yasuo Ohtomo

Daisuke Sasaki

Nobuaki Kawasoe

Yoshiharu Yoshizawa

Shigeki Kawaai

Masaki Tosaka

Noboru Morita

Koji Nakamuta

Hirotomo Izumi

Daisuke Usui

Michio Hibi

A clock data recovery circuit includes a circuit that receives a data signal for which each of a plurality of potential levels is associated with a value of 2 bits or more, based on a result of a first comparison that compares the 3 or more first thresholds with the data signal at timing synchronized with a clock signal; a circuit that outputs a result of a second comparison that compares the data signal with a second threshold at the timing; a circuit that generates a phase difference signal indicating whether to advance or delay a phase of the clock signal, based on the result of the determination and the result of the second comparison; a filter that generates a phase adjusted value indicating an adjustment amount of the phase, based on the phase difference signal; and a circuit that adjusts the phase based on the phase adjusted value.

CDR circuit and receiver of multilevel modulation method

A reception circuit includes: a first equalizer configured to equalize a reception waveform; a second equalizer configured to equalize an input waveform from the first equalizer; a monitor configured to monitor magnitude of the input waveform; and a controller configured to generate a gain control code used for setting a gain of the first equalizer and a threshold voltage control code used for setting a threshold voltage to be compared with the input waveform in the second equalizer, in accordance with a monitoring result of the magnitude obtained by the monitor.

Reception circuit, receiver, and reception control method

A Mach-Zehnder optical modulator includes: a Mach-Zehnder interferometer that includes first and second arms formed on a silicon substrate, and a controller that controls bias current of the first and second arms. The controller controls the bias current of the first and second arms respectively to be a first offset value. The controller repeatedly executes a current adjustment process to increase the bias current of the first arm until a gradient of a phase shift amount of the first arm with respect to the bias current of the first arm reaches a target value. The controller controls the bias current of the second arm to be a second offset value that is smaller than the first offset value. The controller repeatedly performs the current adjustment process to increase the bias current of the first arm until a phase difference of the Mach-Zehnder interferometer reaches a target phase difference.

Mach-zehnder optical modulator

An optical transmitter includes an optical modulator that includes a first phase shifter for a most significant bit, a second phase shifter for a least significant bit, and a third phase shifter for fine adjustment, the first phase shifter, the second phase shifter, and the third phase shifter are disposed along an optical waveguide, and a drive circuit that includes a first driver that drives the first phase shifter, a second driver that drives the second phase shifter, and a third driver that drives the third phase shifter, wherein a drive polarity of the third driver is adjustable in a positive direction and a negative direction, and the third phase shifter adjusts an amount of phase change of the optical modulator in a positive direction or a negative direction based on a drive voltage inputted from the third driver.

Optical transmitter

A circuit includes a calculation circuit configured to calculate a noise power of a predetermined-training-sequence pattern repeatedly included in a first signal input into an adaptive equalizer, based on a second signal obtained by compensating the first signal by a compensation circuit, a channel-estimation value based on the second signal, and the predetermined-training-sequence pattern; and an average circuit configured to obtain an average value of estimation values of frequency offsets based on the predetermined-training-sequence pattern having the noise power equal to or smaller than a predetermined power, among estimation values of frequency offsets based on the predetermined-training-sequence pattern, wherein the compensation circuit is configured to compensate a frequency offset of the predetermined-training sequence pattern based on the average value and thereby obtain the second signal, and the adaptive equalizer is configured to perform adaptive-equalization processing of the first signal with a setting value based on the second signal.

Adaptive equalization circuit, digital coherent receiver, and adaptive equalization method

A signal processing apparatus includes: a filter; and a filter control circuit, wherein the filter control circuit is configured to: detect a power of signals output from the filter; determine one of a plurality of numerical ranges to which the power belongs; update a filter coefficient of the filter according to a determination result; count a number of the signals having the power of a first value or more; set an invalid area which becomes a target not to be determined for each of one or more boundaries between the plurality of numerical ranges when the number of the signals becomes a second value or more; and control a width of the invalid area based on the number of signals.

Signal processing apparatus, signal processing method, and signal processing system

A receiving device that converts, to a digital signal, a signal in which signal light from an optical transmission path and local oscillation light are mixed, so as to perform digital signal processing, the optical communication receiving device comprising: a frequency offset compensation unit configured to calculate a frequency offset of the digital signal and to, based on the frequency offset, compensate for a phase of the digital signal; a carrier phase recovery unit configured to calculate a carrier phase of the digital signal whose phase is compensated for in the frequency offset compensation unit; and a residual frequency offset detection unit configured to calculate an average of differences in the carrier phase, and to output the average as a residual frequency offset, wherein the frequency offset compensation unit is configured to correct the frequency offset using the residual frequency offset output by the residual frequency offset detection unit.

Optical communication receiving device and frequency offset compensation method

A frequency offset estimation circuit estimates a frequency offset that indicates a difference between a carrier frequency of a received optical signal and a frequency of a local oscillation light used to recover a transmission signal from the received optical signal. The frequency offset estimation circuit includes: a phase difference detector configured to detect a phase difference due to the frequency offset between a first symbol and a second symbol that is transmitted after the first symbol by a specified symbol interval based on a phase of the first symbol and a phase of the second symbol; an estimator configured to estimate the frequency offset based on the phase difference detected by the phase difference detector; and a symbol interval controller configured to specify the symbol interval based on the frequency offset estimated by the estimator.

Frequency offset estimation circuit and frequency offset estimation method

An optical receiving device includes: an adaptive equalizer that includes a position estimation unit configured to estimate, based on a first signal component and a second signal component of a reception signal generated by reception of a training sequence pattern transmitted from an optical transmitter, a symbol position of the reception signal, and generates an estimated symbol position, a delay unit configured to provide a delay difference between the first signal component and the second signal component, a control unit configured to set a plurality of symbol displacement amount candidates of displacement amounts for the estimated symbol position, causes the delay unit to generate a plurality of delay differences, and generates a channel estimation symbol position used for channel estimation, and an error rate calculation unit configured to calculate an error rate of the signal restored by an adaptive equalization unit.

Optical receiving device

A signal processing device includes: a plurality of multipliers configured to obtain a first multiplication result by multiplying a tap coefficient by 1/&#x221a;2; a plurality of mappers configured to output a mapping result based on a first mapping coefficient and a digital input signal; and a plurality of first selectors configured to select the first multiplication result based on the mapping result.

Signal processing device, signal processing method, and communication device

A communication device includes a storage unit that stores a predetermined eye mask pattern indicating a receivable range, a receiving unit that receives data from the other communication device, a waveform comparing unit for comparing a waveform of the received data with the eye mask pattern to generate comparison result data and a transmission unit for transmitting the comparison result data to the other communication device.

Communication device and communication system

An equalizer characteristics optimizing method includes acquiring a recovery clock timing from a reception signal; acquiring a predetermined sampling clock timing with respect to the recovery clock timing; latching the reception signal at the recovery clock timing; latching the reception signal at the sampling clock timing; comparing logic values obtained in the latching steps; collecting, after changing a characteristics setting of an equalizer, logic value comparison result data by repeating the recovery clock acquiring step, the acquiring of the sampling clock timing, the latching of the reception signal at the individual clock timings, and the comparing of the logic values, using the changed characteristics setting; and determining an optimum characteristics setting of an equalizer based on the collected logic value comparison result data.

Equalizer characteristics optimizing method and transmission system

A variable delay circuit being able to change a delay amount from when a signal is inputted to when the signal is outputted has a first delay section delaying the signal by a first delay amount, a second delay section delaying the signal by a second delay amount greater than the first delay amount, and a delay amount selector selecting a signal route where the delay amount is a sum of the first delay amount and the second delay amount when the delay amount exceeds a maximum delay amount delayable by the first delay amount section. The delay amount from when a signal is inputted to when the signal is outputted can be set in a wide range, while suppressing the circuit scale.

Variable delay circuit, memory control circuit, delay amount setting apparatus, delay amount setting method and computer-readable recording medium in which delay amount setting program is recorded

The transmission control unit of the device transmits sample data while changing the setting of output amplitude and emphasis of the transmitter within a prescribed range. The transmission processing unit of the device generates an eye diagram from the sample data received by the receiver, detects receivable phase-range data from the eye diagram, and transmits the same. The optimization processing unit of the device writes the phase-range data transmitted from the device into the table in correspondence to the output amplitude and emphasis of which the setting has been changed, determines optimum values of output amplitude and emphasis from the table obtained upon the completion of setting change within the prescribed range, and sets the same in the transmitter of the device. Then, the device, serving as the transmitting side, determines optimum values of output amplitude and emphasis of the transmitter and sets the same.

Device having communication function, method for automatically adjusting transmitter, system and program

To provide a serial transfer interface for realizing a transmission of a stable and high-quality signal although there are characteristic variances due to an environment change and an LSI process, a serial transfer interface is provided at least with a signal waveform correction unit for correcting the distortion of a signal waveform, a latch unit for latching the signal waveform with a synchronous clock and outputting it to a subsequent circuit, a filter characteristic adjustment unit for changing the filter characteristic of the signal waveform correction unit in a predetermined range, a clock generation unit for generating the synchronous clock having a desired phase, and a pattern discrimination unit for detection of a test pattern and control of the filter characteristic adjustment unit and the clock generation unit.

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Fuchu, Japan

Manabu Yamazaki