Fujitsu Corporation

Manabu Tsuchida

Masanobu Yoshida

Mitsuo Higuchi

A voltage supply level detecting circuit comprising a P-channel MIS transistor and an N-channel MIS transistor, the P-channel and N-channel MIS transistors being connected in series between the variable voltage supply and ground, and the gates of the P-channel and N-channel MIS transistors being connected to a fixed voltage supply.

Voltage supply level detecting circuit

A programmable read-only memory device comprising a memory cell transistor which has a floating gate and a control gate formed above the floating gate. The programmable read-only memory device further comprises a means for delaying the application timing of a high voltage to the control gate from that of a high voltage to the drain of the memory cell transistor when a data programming operation is performed by applying the high voltage to the control gate and the drain of the memory cell transistor, thereby ensuring reliable a data write operation even at a low programming voltage.

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Yokohama, Japan

Manabu Tsuchida