Fuji Electric Co., Ltd.

Fuji Electric Holdings Co., Ltd.

National Institute of Advanced Industrial Science and Technology

Fuji Electric Systems Co. Ltd.

Fuji Electric Device Technology Co., Ltd.

Mitsubishi Electric Corporation

Manabu Takei

Yusuke Kobayashi

Shinsuke Harada

Haruo Nakazawa

Tatsuya Naito

Michio Nemoto

Kazuo Shimoyama

Tatsuhiko Fujihira

Akio Nakagawa

Yuichi Onozawa

Akio Sugi

Yoshiyuki Yonezawa

Noriyuki Iwamuro

Koh Yoshikawa

Naoki Kumagai

Naoyuki Ohse

Setsuko Wakimoto

Kouta Takahashi

Mitsuru Sometani

Shinji Fujikake

Akihiro Koyama

Ryuji Yamada

Hidekazu Tsuchida

Koji Nakayama

Yasuhiko Onishi

Kazuhiro Mochizuki

Takeshi Tawara

Mutsumi Kitamura

Satoki Takizawa

Yasushi Miyasaka

Shinichiro Matsunaga

Tomonori Mizushima

Kohei Adachi

Ryoji Kosugi

Kensuke Takenaka

Youichi Shindou

Kouichi Murata

Yuji Kiuchi

A silicon carbide semiconductor device has an active region and a termination structure portion disposed outside of the active region. The silicon carbide semiconductor device includes a semiconductor substrate of a second conductivity type, a first semiconductor layer of the second conductivity type, a second semiconductor layer of a first conductivity type, first semiconductor regions of the second conductivity type, second semiconductor regions of the first conductivity type, a gate insulating film, a gate electrode, a first electrode, and a second electrode. During bipolar operation, a smaller density among an electron density and a hole density of an end of the second semiconductor layer in the termination structure portion is at most 1×10/cm.

Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device

A semiconductor device that includes a SiC semiconductor substrate; a SiC epitaxial layer having an impurity concentration lower than that of the SiC semiconductor substrate; a first semiconductor layer including first semiconductor pillars and second semiconductor pillars; a second semiconductor layer; a device active region; a termination region; a channel stopper region having an impurity concentration higher than that of the SiC epitaxial layer; and a plurality of first chip end portions and a plurality of second chip end portions, and a surface of the first side surface is covered with an impurity region having an impurity concentration higher than those of the first semiconductor pillar and the SiC epitaxial layer and is connected to the channel stopper region.

Semiconductor device

A vertical MOSFET having a trench gate structure includes an n-type drift layer and a p-type base layer formed by epitaxial growth. In the n-type drift layer, an n-type region, a first p-type region, and a second p-type region are provided. A metal film of a trench SBD is connected to a source electrode; and a p-type region is provided between the source electrode and the p-type base layer.

A first side wall and a second side wall of a trench are each an a-plane having high carrier mobility. Along the first side wall of the trench, a gate insulating film is provided. A gate electrode is provided in the trench, and across the gate insulating film, opposes a portion of a p-type base region between an n-type source region and an n-type current spreading region. Along the second side wall of the trench, a conductive layer is provided. The conductive layer, at the second side wall of the trench, forms Schottky contacts with a p-type contact region, the p-type base region, and the n-type current spreading region. The trench has a bottom corner portion that is at the second side wall and encompassed by a p-type region that is provided in the n-type current spreading region so as to be separated from the p-type base region.

In an n-type current diffusion region, a first p-type region underlying a bottom of a trench (gate trench) is provided. In the n-type current diffusion region, a second p-type region is provided between adjacent trenches, separated from the first p-type region and in contact with the p-type base region. In the p-type base region, near a side wall of the trench, a third p-type region is provided a predetermined distance from the side wall of the trench and is separated from the first and the second p-type regions. The third p-type region extends in a depth direction, substantially parallel to the side wall of the trench. A drain-side end of the third p-type region is in contact with the n-type current diffusion region or protrudes a predetermined depth from the interface of the p-type base region and the n-type current diffusion region toward the drain.

A vertical MOSFET having a trench gate structure includes an n-type drift layer and a p-type base layer formed by epitaxial growth. In the n-type drift layer, an n-type region, first p-type regions, and a second p-type region are provided. In a region opposing, in a depth direction, a gate electrode pad connected to a gate electrode, the first p-type regions are provided with intervals therebetween along a width direction of the trench gate.

Semiconductor device having semiconductor regions with an interval therebetween in a gate pad region

Plural trenches are provided in a semiconductor substrate. First p-type regions underlie bottoms of the trenches. A MOS gate is embedded in first trenches of the trenches and one unit cell of a trench-gate-type MOSFET is configured. One unit cell of a trench-type SBD is constituted by a Schottky junction formed by an n-type current spreading region and a conductive layer embedded in a second trench of the trenches. Between second trenches in which the trench-type SBD is embedded, at least two of the first trenches in which a MOS gate is embedded are disposed. A sum of widths of all first p-type regions disposed in a MOS cell region C' that is substantially half of a region between the adjacent second trenches is in a range of about 2 &#x3bc;m to 8 &#x3bc;m.

Semiconductor device having a schottky barrier diode

In mesa regions between adjacent trenches disposed in an n-type drift layer and in which a first gate electrode is disposed via a first gate insulating film, a p-type base region and a floating p-type region of which a surface is partially covered by a second gate electrode via a second gate insulating film are disposed. An emitter electrode contacts the p-type base region and an n-type emitter region, and is electrically isolated from first and second gate electrodes and the floating p-type region by an interlayer insulating film covering the first and second gate electrodes and a portion of the floating p-type region not covered by the second gate electrode. Thus, turn-on dV/dt controllability by the gate resistance Rg may be improved.

Method of manufacturing a semiconductor device having two types of gate electrodes

On a front surface of a semiconductor base, a first n-type drift region, a second n-type drift region, and a third n-type drift region are provided. In the front surface of the semiconductor base, a gate trench is provided penetrating the n-type source region and the p-type base region, and reaching the second n-type drift region. Between adjacent gate trenches, a contact trench is provided that penetrates the n-type source region, the p-type base region, and the second and third n-type drift regions, and that reaches the p-type semiconductor region. A source electrode embedded in the contact trench is in contact with the p-type semiconductor region at the bottom and the corners of the contact trench and forms a Schottky junction with the third n-type drift region and the second n-type drift region at a side wall of the contact trench.

Semiconductor device and method of manufacturing the semiconductor device

In a trench-gate vertical MOSFET, an n-type drift layer and p-type base layer are epitaxially grown on an nsilicon carbide substrate, and an nsource region and pcontact region are provided inside the p-type base layer. The first source electrode contacts the nsource region, and the second source electrode contacts the pcontact region. The first source electrode and second source electrode are separated from each other.

Silicon carbide semiconductor device, method of manufacturing silicon carbide semiconductor device, and method of controlling silicon carbide semiconductor device

A semiconductor device, including a first groove, a second groove and a first impurity region provided on a semiconductor substrate, a second impurity region provided in the first impurity region, a gate electrode provided in the first groove, a first insulating film provided between the first groove and the gate electrode, a second insulating film provided in the second groove, and a third insulating film provided astride tops of the first groove and the second groove. Each of the first and second insulating films has a lower half portion that is thicker than an upper half portion thereof. The lower half portions of the first and second insulating films are connected. The gate electrode has first and second portions thereof respectively contacting the lower and upper half portions of the first insulating film, a width of the first portion being narrower than a width of the second portion.

Semiconductor device and method of manufacturing semiconductor device

A method of evaluating a semiconductor device having an insulated gate formed of a metal-oxide film semiconductor. The semiconductor device has a high potential side and a low potential side, and a threshold voltage that is a minimum voltage for forming a conducting path between the high and low potential sides. The method includes determining a variation of the threshold voltage at turn-on of the semiconductor device by continuously applying an alternating current (AC) voltage to the gate of the semiconductor device, a maximum voltage of the AC voltage being equal to or higher than the threshold voltage of the semiconductor device.

Method of evaluating semiconductor device and apparatus for evaluating semiconductor device

In an active region, a contact trench in which a source electrode is embedded is provided. In a boundary region between the active region and the edge termination region, a tapered trench is provided. A second p-type base region is provided along an inner wall of the contact trench and extends to the boundary region to be provided along a base front surface and an inner wall of the tapered trench. An angle &#x3b8;of the side walls of the tapered trench with respect to a substrate front surface is smaller than an angle &#x3b8;of the side walls of the contact trench with respect to the substrate front surface. At a second mesa portion between the tapered trench and a step of the edge termination region, a gate runner is arranged on the base front surface, via a field oxide film.

Semiconductor device having first and second gate electrodes

After a trench is formed, a deposition film is formed on the front surface of a base material and an inner wall of the trench such that a thickness of a portion of the deposition film covering the front surface of the base material is greater than a thickness of a portion of the deposition film covering the inner wall of the trench. The total thickness of the deposition film is then reduced until the inner wall of the trench is exposed, leaving only the portion of the deposition film covering the front surface of the base material. By performing sacrificial oxidation in this state, the thermal oxide film caused by thermal oxidation barely grows at the interface of the front surface of the base material and the deposition film, and thus the thickness of an n+ source region is mostly maintained.

Growing community of inventors

Shiojiri, Japan

Manabu Takei