Ngk Spark Plug Company, Limited

Manabu Sato

Jun Otsuka

Motohiko Sato

Kazuhiro Hayashi

Kenji Murakami

Shinji Yuri

Akifumi Tosa

Motonobu Kurahashi

Hiroshi Yamamoto

Hidetoshi Mizutani

Toshitake Seki

Seiji Ichiyanagi

Yusuke Kaieda

Masahiko Okuyama

Kazuhiro Urashima

Hiroshi Sumi

Yasuhiko Inui

Masaki Muramatsu

Takamichi Ogawa

Syouji Ono

Tetsuo Suehiro

Jyunichi Ichikawa

Keiji Takagi

Yukihiro Kimura

Fumio Mizuno

Katsuya Yamagiwa

Hisahito Kashima

Kazuhisa Itakura

Yasuhiro Sugimoto

Takashi Kasashima

Eiji Kodera

Takashi Oba

Masahiko Matsumiya

Takeo Kinoshita

Masashi Suzumura

Tsutomu Sakai

Kazuyuki Fujii

Makoto Baba

Kozo Yamazaki

Kohki Ogawa

Yasuhiro Tsujimura

Junichi Ito

Hidetoshi Mitzutani

A dielectric structure including a metal foil, a dielectric layer and a conductor layer provided in this order, wherein the metal foil has a thickness of from 10 to 40 &#x3bc;m, the dielectric layer has a thickness of from 0.3 to 5 &#x3bc;m, and the conductor layer has a thickness of from 0.3 to 10 &#x3bc;m. The dielectric structure has plural vias which are separated from each other, and which penetrate through both of the dielectric layer and the conductor layer. The vias of the dielectric layer have different diameters which are in a range of from 100 to 300 &#x3bc;m, a diameter of each of the vias of the conductor layer is larger than a diameter of a corresponding via of the dielectric layer by 5 to 50 &#x3bc;m, and a minimum via pitch is from 100 to 350 &#x3bc;m.

Method of manufacturing a dielectric structure

A wiring substrate in which a capacitor is provided, the capacitor comprising a capacitor body including a plurality of dielectric layers and internal electrode layers provided between the different dielectric layers, wherein said capacitor body has, in at least one side face of said capacitor body, recesses extending in a thickness direction of said capacitor body from at least one of a first principal face of said capacitor body and a second principal face positioned on the side opposite to the first principal face.

Capacitor to be incorporated in wiring substrate, method for manufacturing the capacitor, and wiring substrate

A capacitor comprising: a capacitor body including a plurality of laminated dielectric layers, a plurality of inner electrode layers which are respectively disposed between mutually adjacent ones of the dielectric layers, a first main surface located in a laminated direction of the dielectric layers, and a second main surface opposite to the first main surface; a first outer electrode formed on the first main surface of the capacitor body and electrically connected to the inner electrode layers; a second outer electrode formed on the second main surface of the capacitor body and electrically connected to the inner electrode layers; a first dummy electrode formed on the first main surface of the capacitor body; and a second dummy electrode formed on the second main surface of the capacitor body.

Capacitor for incorporation in wiring board, wiring board, method of manufacturing wiring board, and ceramic chip for embedment

A capacitor is provided having a tough surface portion which prevents cracking that tends to occur when the capacitor is built-in or surface-mounted on a wiring board. A ceramic sintered body of the capacitor includes a capacitor forming layer portion, a cover layer portion and an interlayer portion. The capacitor forming layer portion has a laminated structure wherein ceramic dielectric layers and inner electrodes connected to a peripheral portion of capacitor via conductors, are alternately laminated. The cover layer portion is exposed at a surface portion of the ceramic body and has a laminated structure wherein ceramic dielectric layers and dummy electrodes not connected to the capacitor via conductors, are alternately laminated.

Capacitor and wiring board including the capacitor

A diplexer provides a high degree of design freedom for satisfying the requirements of electric characteristics so as to realize desired characteristics and at the same time can be downsized and a multiplexer is realized by using such a diplexer. The diplexer includes a filter having a first pass band and a filter having a second pass band with a frequency band at least twice as high as the frequency band of the first pass band, the filter having the first pass band being a filter of the lumped constant type, the filter having the second pass band being a filter of the distributed constant type.

Diplexer and multiplexer using the same

It is possible to generate an additionally attenuation pole in a laminate type band pass filter without adding an attenuation circuit and improve the attenuation characteristics of the laminate type band pass filter by independently controlling the frequencies of the attenuation poles. A diplexer is realized by using at least such a filter. The laminate type band pass filter includes a plurality of first resonators adapted to resonate in a predetermined pass band and arranged in a laminate, the first resonators being mutually electromagnetic field coupled, each of the first resonators having a first inductor conductor, a second inductor conductor and a conductor to be capacitive-coupled to a grounding conductor, the second inductor conductor and the conductor to be capacitive-coupled to the grounding conductor forming a second serial resonator in each of the first resonators, the notch frequency of the second serial resonator being set in a frequency band higher than the resonance frequency band of the first resonator.

Laminate type band pass filter and diplexer using the same

A circuit board ('&#x2033;) comprising: a board core () having a main core surface () and a rear core surface (); a ceramic capacitor (&#x2033;&#x2033;&#x2033;) having a main capacitor surface () and a rear capacitor surface (), having a structure in which a first inner electrode layer () and a second inner electrode layer () are alternately stacked with a ceramic dielectric layer () interposed therebetween, and having a plurality of capacitor function units () being electrically independent from each other, the ceramic capacitor (&#x2033;&#x2033;&#x2033;) being buried in the board core () in a state where the main core surface () and the main capacitor surface () are directed in a same direction; and a buildup layer () having a structure in which an interlayer insulating layer () and a conductor layer () are alternately stacked on the main core surface () and the main capacitor surface () and having a semiconductor integrated circuit device mounting region () for mounting a semiconductor integrated circuit device () having a plurality of processor cores () on a surface () of the buildup layer (), wherein the plurality of capacitor function units () are capable of being electrically connected to the plurality of processor cores (), respectively.

Ceramic capacitor

Dielectric lamination structure, manufacturing method of a dielectric lamination structure, and wiring board including a dielectric lamination structure

A wiring board comprising: a board core () having a core main surface () and a core reverse surface (); a capacitor (A,B,C,D,E,F,G,H,J,'&#x2033;&#x2033;) having a capacitor main surface () and a capacitor reverse surface () and having a structure in which first inner electrode layers () and second inner electrode layers () are alternately laminated and arranged via a dielectric layer (), the capacitor (A,B,C,D,E,F,G,H,J,&#x2032;&#x2033;&#x2033;) being accommodated in the board core () in a state in which the core main surface () and the capacitor main surface () are oriented on a same side; and a wiring laminated portion () having a structure in which interlayer insulating layers () and conductor layers () are alternately laminated on the core main surface () and the capacitor main surface (), wherein an inductor () or a resistor () is formed on or in the capacitor (A,B,C,D,E,F,G,H,J,&#x2032;&#x2033;&#x2033;).

Wiring board and capacitor

A via array capacitor including a capacitor body having a first main surface and a second main surface and having a structure in which dielectric layers and inner electrode layers are alternately laminated; a plurality of via conductors which conduct the inner electrode layers to each other and are, as a whole, arranged in array form; and metal-containing layers which are disposed on at least one of the first main surface and the second main surface, wherein a total volume of the inner electrode layers and the metal-containing layers included in the via array capacitor is from 45 vol.% to 95 vol.% of a volume of the via array capacitor.

Via array capacitor, wiring board incorporating a via array capacitor, and method of manufacturing the same

In order to provide a built-in capacitor type wiring board capable of preventing misalignment of the capacitor, a capacitor built-in type wiring board is provided which includes a core board; a multilayer portion disposed on at least one side of the core board and formed by a plurality of interlayer insulating layers; and a plurality of conductor layers alternately laminated on the core board. The capacitor is of a chip-like shape with first and second main surfaces and includes a dielectric layer; electrode layers laminated on the dielectric layer; and a hole portion opening at least at the second main surface. The capacitor is embedded in the interlayer insulating layers so that the second main surface faces the core board.

Built-in capacitor type wiring board and method for manufacturing the same

Growing community of inventors

Nagoya, Japan

Manabu Sato