Sharp Kabushiki Kaisha Corporation

Manabu Onozaki

Manabu Yumoto

Tsuyoshi Muramatsu

Atsushi Yamashita

Yasufumi Itoh

Shinichi Yoshida

Toshiya Okamoto

Hiroshi Tanaka

Kazuo Tamaki

Ken Sumitani

Masanobu Okano

Tsuyoshi Ono

Daisuke Azuma

Motoki Takase

Mitsuhisa Ohnishi

Masataka Miyata

Akihisa Yamada

Takashi Horiyama

Ricardo T Shichiku

Hiroshi Umeda

Hiroyuki Nabesawa

Futoshi Miyamae

Yusuke Shibata

Takuji Uneyama

Yasuhiro Matsuura

Masayuki Itoh

Takayoshi Tanaka

To provide a circuit for reducing an afterglow of secondary light, a circuit includes an LED () which includes an LED chip () and a KSF phosphor (), and a first output circuit () and a second output circuit () which are coupled to a cathode (C). When a PWM signal goes to 'H', the first output circuit is driven thereby making IF flow from the cathode. When the PWM signal goes to 'L', the first output circuit stops driving, and the second output circuit makes an offset current flow from the cathode.

Light emitting diode drive device and illumination device

An illumination device () includes a light guide plate () and a light source unit () which includes a substrate () and a plurality of LED chips () disposed on the substrate (), and which is disposed in a position at which emitted light of the LED chips () enters a light entrance portion () of the light guide plate (). The LED chips () are disposed to form a plurality of rows on the substrate (), and are disposed to line up in a direction which orthogonally intersects the rows between each of the rows.

Illumination device, illumination equipment, and display device

The present invention makes it possible to (i) obtain a sufficient and uniform luminance on an entire surface, which is irradiated with light, of a light guide plate and (ii) achieve a reduction in cost. LED light source substrates () and () are each configured to emit light having a first luminance gradient on an edge of a range, to be irradiated with light, which first luminance gradient is smaller than a second luminance gradient of light having a substantially uniform luminance on an entire range to be irradiated with light.

Edge-light type planar light source device

A light emitting module board which is compatible with a plurality of screen sizes and is used for a backlight apparatus of a liquid crystal display panel is provided. A light emitting module includes a first connectorand a second connector, each including a plurality of cathode terminals and at least one anode terminal, at each end of the board, and can be connected to another one to each other through the connectors in multi-level. A cathode wiringfor supplying a cathode control signal includes first cathode wirings which connect the cathode terminals of the first connector and light emitting bodies to supply a control signal to the light emitting bodies in the light emitting module, and second cathode wirings which connect the cathode terminals of the first and second connectors to supply a control signal to the light emitting bodies on a downstream light emitting module.

Light emitting module, light emitting module unit, and backlight system

A light source device which is used as the backlight device and does not generate sound is provided. One or more flat substrates each having a light emitting element on its surface side are supported by a chassis having a conductive flat plate surface so that back surfaces of the substrates are opposed to the flat plate surface. The substrate comprises first wiring conductive thin films on a surface side of an insulation substrate, and one or more second radiating or wiring conductive thin films on a back surface side of the insulation substrate. Two terminals of the light emitting element are connected to the two adjacent first conductive thin films. A potential of at least one of the second conductive thin films is fixed to have a constant potential difference or preferably fixed to the same potential with respect to that of the flat plate surface of the chassis.

Light source device

An image collating apparatus includes a storage device and a processor. The storage device stores data representing a sensing image, data representing a template image, and a program. The processor detects exclusion areas in the sensing image to be excluded from the image collation operation based on classification of image patterns. The processor determines whether or not the sensing image and the template image are derived from the identical object by performing template-matching operations to evaluate similarity between the template image and partial images of the sensing image in different levels with increasing the size of area covered by the partial image to be matched with the template image level by level. At least in one level the processor performs the template-matching operation with respect to the partial image where the exclusion areas are excluded.

Image collating apparatus, image collating method, image collating program product, and computer readable recording medium recording image collating program product

When first and second images are input, a partial image feature calculating unit calculates feature values of partial images of the two images. A maximum matching score position searching unit searches for a position of the second image that attains to the highest matching score with each of the partial images of the first image. A movement-vector-based similarity score calculating unit calculates similarity between the first and second images, using information related to that partial image whose movement vector has direction and length within a prescribed range, which movement vector representing positional relation between a reference position for measuring, for each of the partial images, the position of the partial image in the first image and the position of the maximum matching score corresponding to the partial image searched out by the maximum matching score position searching unit. The images as the object of collation may belong to the same category classified based on the feature values.

Image collating apparatus, image collating method, image collating program and computer readable recording medium recording image collating program

An image matching device capable of matching two images performs the following processes in order to shorten a processing time and reduce power consumption. Template matching is performed between a first image and a second image using a predetermined partial image of the first image, and the similarity between the two images is calculated. The similarity thus obtained is compared with a predetermined threshold. Only upon determination that the similarity obtained and the predetermined threshold neither coincide not fail to coincide with each other, the partial image used for template matching is gradually increased until the similarity and the predetermined threshold come to coincide or fail to coincide with each other. Then, template matching is performed again and the similarity between them is calculated.

Image matching device capable of performing image matching process in short processing time with low power consumption

An arbitration circuit adjusts timings of a write request signal from a first external device and a read request signal from a second external device. An RAM performs data write/data read in response to the external write request/read request. A next-state function is provided, which has a function to calculate a write address/read address to be input to the RAM in response to the external write request/read request, and a function to accurately count data stored in a FIFO.

Self-synchronous FIFO memory device having high access efficiency, and system provided with interface for data transfer using the same

The data driven type information processing system has a branch unit and a junction unit in the input and output stages thereof, and includes a plurality of data driven type processors between the branch unit and the junction unit. The branch unit, the junction unit and the plurality of data driven type processors are coupled to one another via transmission paths. Each of the data driven type processors can process a unique instruction system. The junction unit collects data packets provided via the transmission paths and outputs the collected data packets to the outside of the system. In operation, when a data packet is provided to the system, the branch unit receives the data packet provided thereto and, according to an instruction code within the received data packet, selects a transmission path connected to a data driven type processor that can process an instruction system corresponding to the instruction code, and sends out the received data packet to the selected transmission path. Upon reception of the data packet via the transmission path, each of the data driven type processors processes the received data packet in a prescribed manner, and, according to the result of the processing and based on the instruction code within the obtained data packet, selects a transmission path connected to a data driven type processor that can process the instruction system corresponding to the instruction code, and sends out the data packet to the selected transmission path.

Data driven type information processing system consisting of interconnected data driven type information processing devices

A data driven processor includes an H register storing output destination information in path connection verification, and a circuit for selectively providing a data packet to one of a plurality of output ports according to a path verification flag and destination information included in an input data packet and the contents of the H register. The processor 250 may further include a circuit for applying a data packet to an image memory unit according to a path verification flag included in the input data packet and the contents of the H register, and a circuit for directly providing to the output processing unit a data packet for testing returned from an image memory unit according to the path verification flag thereof. A data driven information processing device including a plurality of data driven processors and a method of verifying a path connection in this data driven information processing device are also disclosed.

Data driven processor, a data driven information processing device, and

In a data driven information processing system including processors which processes datapackets, a method of verifying identification information allocated to the processors includes the following steps: previously specifying a path for a datapacket via the processors; providing the data driven information processing system with information specifying the number of the other processors for the datapacket to pass through until the packet reaches a certain processor from the input of the system in the path, and a datapacket for identification which stores an identification data verification instruction; a first transmission step of transmitting the datapacket for identification to the processor along the specified path while updating information indicating the number of processors and applying the packet to the processor; a step of producing a result datapacket which stores the identification data of the processor for output in the specified path; a second transmission step of transmitting the result datapacket along the specified path for output; and a step of verifying identification data stored in the output result datapacket.

Method of verifying identification data in data driven information

Data packet groups to be input to a data driven type information processor are sequentially allotted generation number data successive in a ring-like manner and the order of input. When two different data packets contend for access at the time of detection of paired data in the information processor, the two generation number data contending for access are compared with each other in terms of the above-described ring-like relationship to determine priority for paired data detection processing based on the comparison result, thereby ensuring that a data packet group input first to the information processor is always given priority for processing.

Data driven information processor with ring comparing comparator

A self-timed clocking transfer control circuit includes a flipflop for storing a transition of a transfer request signal to an L level and outputting an H level signal, an inverter for applying a transfer acknowledge signal to a preceding stage, a 5-input NAND gate, and a second signal output circuit for applying a transfer request signal to a succeeding stage in response to a transition of the output of the 5-input NAND gate to the L level. The 5-input NAND gate does not output the L level unless the transfer request signal from the preceding stage, the output of the flipflop, the transfer acknowledge signal from the succeeding stage, the transfer request signal output by the self-timed clocking transfer control circuit itself, and the prohibition signal are all in the H level. Setting the prohibition signal to the L level, self-synchronous type transfer control can be prohibited. A circuit for generating such a prohibition signal based on a signal for setting an operational mode, a clock signal, and the transfer request signal from the preceding stage may additionally be provided.

Self-timed clocking transfer control circuit

A data transmission path includes a transfer control circuit and a data hold circuit. The transfer control circuit outputs a transmission signal for transferring the data held by the data hold circuit to a data transmission path in a succeeding stage in response to an existence of data to be transferred in the data hold circuit, non-existence of data in the data transmission path in the succeeding stage and an externally applied timing signal.

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Osaka, Japan

Manabu Onozaki