Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Socionext Inc.

Manabu Kuroda

Tokuzo Kiyohara

Hiroshi Mizuno

Hideyuki Ohgose

Junji Michiyama

Kozo Kimura

Tomohiko Kitamura

Ryoji Yamaguchi

Yoshihiro Koga

Akifumi Yamana

Kazutoshi Funahashi

Nobuhiko Yamada

Yoshihiro Nakahara

Keisuke Yorioka

Tetsuya Tanaka

Takeshi Tanaka

Shuji Miyasaka

Masato Suzuki

Taketo Heishi

Hideshi Nishida

Hajime Ogawa

Kouji Nakajima

Hazuki Okabayashi

Noboru Asai

Osamu Furuya

Masakazu Kanda

An integrated circuit for video/audio processing in which design resources obtained by development of video/audio devices can also be used for other types of video/audio devices. The integrated circuit includes a microcomputer that includes a CPU, a stream input/output for inputting/outputting a video and audio stream to and from an external device, a media processor that executes the media processing including at least one of compressing and decompressing the video and audio stream inputted to the stream input/output, an AV input/output that converts the video and audio stream subjected to the media processing by the media processor into video and audio signals and outputting these signals to the external device. A memory interface controls a data transfer between the microcomputer, the stream input/output, the media processor and the AV input/output and an external memory.

Integrated circuit with multipurpose processing and for video/audio processing optimization

An integrated circuit for video/audio processing in which design resources obtained by development of video/audio devices can also be used for other types of video/audio devices. The integrated circuit includes a microcomputer that includes a CPU, a stream input/output for inputting/outputting a video and audio stream to and from an external device, a media processor that executes the media processing including at least one compressing and decompressing the video and audio stream inputted to the stream input/output, an AV input/output that converts the video and audio stream subjected to the media processing by the media processor into video and audio signals and outputting these signals to the external device. A memory interface controls a data transfer between the microcomputer, the stream input/output, the media processor and the AV input/output and an external memory.

Integrated circuit for video/audio processing

A coding section encodes plural pieces of video data sequentially. A measuring section measures a time period which the coding section has used for coding video data. When the time period measured by the measuring section is judged to be longer than a predetermined time based on a frame rate of the video data, a control section selects at least one piece of video data to be coded after the video data coded by the coding section out of the plural pieces of video data and generates a predetermined bit stream instead of coded data of the thus selected video data without allowing the coding section to encode the selected data.

Video coder, coding controller, and video coding method

An address generating unitgenerates a different write start address (w_adr) of a picture memorydepending on an aspect ratio and/or a display plane position of a motion picture to be displayed. A picture writing unitwrites data to the picture memory, starting at the calculated write start address (w_adr). A picture reading unituses the write start address (w_adr) as a read start address (r_adr) and reads data from the picture memory, starting at the read start address (r_adr).

Motion picture display device

A data processing apparatus stops a supply of data to a buffer when the buffer becomes full, and thereafter performs processing such as moving to a low-power mode and switching execution tasks. The data processing apparatus then reverts from the low-power mode and resumes execution of a task for supplying data to the buffer when a predetermined reversion condition is satisfied. The predetermined reversion condition is that, for example, processing with respect to data in a predetermined data cluster is completed, a predetermined time period has elapsed, or a cycle handler notifies an event occurrence.

Data processing apparatus having improved buffer management

A semiconductor device has a processor, a first memory unit accessed by the processor, a plurality of page memory units obtained by partitioning a second memory unit which is accessible by the processor at a speed higher than the speed at which the first memory unit is accessible such that each of the page memory units has a storage capacity larger than the memory capacity of a line composing a cache memory, a tag adding, to each of the page memory units, tag information indicative of an address value in the first memory unit and priority information indicative of a replacement priority, a tag comparator for comparing, upon receipt of an access request from the processor, the address value in the first memory unit with the tag information held by the tag, and a replacement control unit for replacing the respective contents of the page memory units.

Memory replacement mechanism in semiconductor device

A processor according to the present invention includes a decoding unit, an operation unit and others. When the decoding unit decodes an instruction 'vxaddh Rc, Ra, Rb', an arithmetic and logic/comparison operation unit and others (i) adds the higher 16 bits of a register Ra to the lower 16 bits of the register Rb, stores the result in the higher 16 bits of a register Rc, and in parallel with this, (ii) adds the lower 16 bits of the register Ra to the higher 16 bits of the register Rb, and stores the result in the lower 16 bits of the register Rc.

Processor executing SIMD instructions

The image processor of the present invention includes: an extracting means, an entropy decoding means, a combining means, and an inverse orthogonal transformation means. Coded data at respective stages in a certain block are extracted by the extracting means, and entropy-decoded by the entropy-decoding means, to obtain coefficient data at the respective stages in the block. The coefficient data at the respective stages are combined by the combining means to obtain coefficient data for the block. The coefficient data is subjected to inverse orthogonal transformation by the inverse orthogonal transformation means, to attain original image data for the block. The above series of processing are performed for all blocks, to attain an original image on the entire screen. The memory capacity required for combining the coefficient data at the respective stages may only be large enough to store coefficient data for one block.

Image processor and image processing method for decompressing progressive-coded compressed image data

Growing community of inventors

Hyogo, Japan

Manabu Kuroda