Renesas Technology Corp.

Hitachi, Ltd.

Renesas Electronics Corporation

Other

Hitachi Communication Technologies, Ltd.

Renasas Electronics Corporation

Manabu Kawabe

Satoshi Tanaka

Yukinori Akamine

Kazuo Watanabe

Masumi Kasahara

Kazuyuki Hori

Nobukazu Doi

Takashi Ishikawa

Katsuhiko Tsunehara

Seishi Hanaoka

Hirotake Ishii

Koji Maeda

Yasuo Shima

Ryoichi Takano

Yoshikazu Nara

Masashi Takada

Shiro Mazawa

Takao Okazaki

Yasuyuki Kimura

Hiroshi Tanaka

May Suzuki

Takanobu Tsunoda

Kiyoshi Kawamoto

Tomoyuki Ono

Tetsuroo Honmura

Irei Kyu

The present invention aims to efficiently calibrate the characteristics of a pair of reception or transmission low-pass filters by a receiving or transmitting circuit. A semiconductor integrated circuit includes an RF receiver that processes an RF reception signal, an RF transmitter that generates an RF transmission signal and a frequency synthesizer. A reception low-pass filter of the RF receiver suppresses undesired components contained in I and Q baseband reception signals. A transmission low-pass filter of the RF transmitter suppresses noise due to D/A conversion, which is contained in I and Q transmission analog baseband signals. A calibration test signal is supplied to the inputs of the pair of reception or transmission low-pass filters. A difference in phase between the pair of filters is detected by a phase detection unit. A calibration controller calibrates a relative mismatch between the cut-off frequencies of the pair of filters.

Semiconductor integrated circuit

This invention provides a wireless transmitter circuit for mobile communication apparatus and this circuit can be configured with fewer components and is suitable for downsizing. A single PLL synthesizer serves as both RF frequency band PLL and IF frequency band PLL among three oscillators for TX, RX and IF frequency bands, which have been required in conventional mobile communication apparatus. The number of necessary oscillators occupying a large area within a chip is reduced and the number of components is decreased. Specifically, circuitry is arranged to generate local oscillation signals for RF and IF frequency bands by frequency dividing the output of a VCO of the RF frequency band PLL.

Wireless transmitter circuit and transceiver using the same

The present invention provides a PLL circuit containing a loop gain circuit capable of suppressing loop gain variation. This PLL circuit includes a counter that is driven by a voltage controlled oscillator within the PLL circuit, an accumulator (ACL) that accumulates the output of the counter, and a comparison operation circuit block that compares the count value of the ACL and the design value pre-stored in a register, and the loop gain of the PLL circuit is detected taking advantage of the fact that the ACL count value is inversely proportional to the loop gain. Based on the detection result, the loop gain is calibrated by correcting the loop gain with a charge pump current, etc. This allows the PLL circuit to maintain stable loop characteristics that will not affect the characteristics variation of each element constituting the PLL.

Phase locked loop circuit

The receiver, which enables rejection of image signals with higher accuracy over wider frequency band, can be provided as a low IF receiver by inputting a calibration signal of frequency f(1&#x2266;i&#x2266;N) before reception of signals and determining the frequency response f(z) to f(z) of a calibrating filter in a filter mismatch calibrating circuit (FIL_CAL)to make zero amplitude and phase mismatches between the I component and Q component of the quadrature demodulation signal at the frequency f.

Method and system for calibrating frequencies-amplitude and phase mismatch in a receiver

To realize a software radio processing with a reduced circuit area by hardware and software which can process transmission and reception, or synchronization and demodulation in time division. There are provided a circuit DRC that can dynamically change a configuration with a structure that can change the configuration at a high speed, a general processor, and an interface for connection with an external device such as an AD converter or a DA converter. Software radio is realized by using a software radio chip that conducts plural different processing such as transmission and reception, or synchronization and demodulation in time division. The different processing during the radio signal processing can be conducted in time division. As a result, the software radio can be realized with a circuit of a reduced area in a software radio system that allocates regions of an FPGA to the respective processing.

Semiconductor integrated circuit and a software radio device

A radio communication apparatus having a radio modem for processing a signal in a radio frequency band, a signal processor for processing a base band of a transmission or reception signal, and a CPU for processing a protocol. The signal processor includes signal processing blocks implemented by programmable software. Each of the signal processing blocks processes a signal of reception signal data input from the radio modem or from a preceding stage of one of the signal processing blocks or a signal of transmission signal data input from the CPU or from the preceding stage of signal processing block on the basis of a control signal input together with the transmission signal data or the reception signal data. The control signal can include information required by all the signal processing blocks in a common format.

Software defined radio and library configuration therefor

A PLL circuit equipped with a loop gain detecting circuit that can suppress the change of the loop gain. When detecting the loop gain, the frequency of the input signal to the second input (IN-) of the phase detector is first changed, and the response corresponding to the change is detected by the output of the voltage locked oscillator. The detection is performed by connecting the output of the voltage locked oscillator with the counter and connecting the output of the counter with the integrator. The phase locked loop characteristics are optimized by performing feedback for the detection result on the value of the charge pump current.

Phase locked loop circuits, offset PLL transmitters, radio frequency integrated circuits and mobile phone systems

A &#x3a3;&#x394; transmitter that permits setting of a loop filter LF, a charge pump current and other factors to the same conditions even if it is operated in a plurality of frequency bands, therefore allows the number of components to be reduced and at the same time enables the angle between the phases of local signals for reception use to be close to exactly 90&#xb0;, which is a feature ensuring robustness against inter-element variations and accordingly suitable for large scale integration, is to be provided. The oscillation frequency of a VCO is set to an even-number multiple of the transmit frequency, and generates transmit signals via a divider. A device that varies the gain according to the amplitude component of modulating signals is added to an amplifier whose input is signals from the VCO, and the transmission of modulating signals involving amplitude modulation, such as EDGE, is thereby made possible.

Sigma delta (&#x3a3;&#x394;) transmitter circuits and transceiver using the same

This invention provides a receiver in which the calibration time by repeated operations to correct phase mismatch and amplitude mismatch between I and Q signals can be reduced. The receiver comprises mixers which convert received RF signals into quadrature modulated IF signals, signal paths which filter and amplify and output the quadrature modulated signals output from the mixers, a calibration circuit which calibrates phase and amplitude mismatches between the I and Q components of the quadrature modulated signals output through the signal paths, a frequency converter which, when the mixers or the signal paths selected output calibration signals with IF frequency instead of the quadrature modulated signals, converts the calibration signals into those with a frequency higher than IF frequency, and an arithmetic operation circuit which calculates phase and amplitude mismatches from the calibration signals output by the frequency converter and outputs calculation results. The calibration circuit executes calibration, using the calculation results.

Receiver, receiving method and portable wireless apparatus

To simplify the configuration of functional modules in a software-defined radio apparatus, and facilitate the development of software. The functional modules have input and output terminals of a common configuration. Distributed timing control is performed so that the functional modules operate in their respective timings, and the functional modules have common input/output signals.

Software-defined radio apparatus

A radio receiver handles a transmitted Walsh sequence having a code length of 'm' as a two-dimensional array of 'a' rows and &#x201c;b&#x201d; columns, and performs a fast Hadamard transform process having a code length of &#x201c;a&#x201d; in the row direction. The absolute values of the results are added in the column direction, and a Walsh number having the maximum receiving power is selected to determine a Walsh sequence having a code length of &#x201c;a.&#x201d; Then, only the identified column is extracted, and a fast Hadamard transform process having a code length of &#x201c;b&#x201d; is applied in the column direction.

Radio receiver

The hardware configuration of a baseband block in a radio communication system is reduced in gate size. Modulation/demodulation processing in a baseband block is divided into a plurality of processing units, which are connected to one another by buffer memories. The hardware gate sizes are reduced by performing processing on a plurality of channels by time division multiplexing at a speed higher than the speed at which received signals are written into the buffer memories.

Growing community of inventors

Hachioji, Japan

Manabu Kawabe