Other

Hitachi, Ltd.

Hitachi Ulsi Systems Co., Ltd.

Manabu Ishimatsu

Goro Kitsukawa

Michihiro Mishima

Toshitsugu Ueda

Hiroshi Yoshioka

Masahito Suzuki

Yoshihiko Inoue

In a device including regular circuits and redundant circuits, a plurality of relievable first wiring lines and a plurality of irrelievable second wiring lines are arranged in the same wiring layer as what constitutes the regular circuits and in the same direction, and at the same time the irrelievable wiring lines are arranged adjoining one another.

Semiconductor integrated circuit device

There is provided a semiconductor memory which allows a redundant memory cell to be disposed at the center while maintaining the continuity of layout units of direct peripheral circuits and allows the total yield of the memory cell and the direct peripheral circuits to be improved. The inventive semiconductor memory is a 64 M-bits or 256 M-bits DRAM using a hierarchical word line structure or a multi-division bit line structure and comprises a main row decoder region, a main word driver region, a column decoder region, a peripheral circuit/bonding pad region, a memory cell array, a sense amplifier region, a sub-word driver region, intersection regions and the like formed on one semiconductor chip.

Semiconductor memory

Growing community of inventors

Fukuoka, Japan

Manabu Ishimatsu