Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Manabu Imahashi

Yasushi Kobayashi

Hiroyoshi Ogura

Masakatsu Nawate

A semiconductor circuit includes: a first diffusion layer formed on a substrate; a second diffusion layer formed in an upper part of the first diffusion layer; a third diffusion layer formed in an upper part of the second diffusion layer; a fourth diffusion layer formed in the upper part of the first diffusion layer; and a fifth diffusion formed below the third diffusion layer. A sum of a shortest distance from the third diffusion layer to the fifth diffusion layer and a shortest distance from the fifth diffusion layer or the lower end of the first diffusion layer to the fourth diffusion layer is smaller than a shortest distance from the third diffusion layer to the fourth diffusion layer. The substrate, the second and the fifth diffusion layer are a first conductivity type and the others are a second conductivity type.

Semiconductor integrated circuit

A semiconductor device includes: an n-type first well diffusion layer; an n-type second well diffusion layer; a p-type source diffusion layer; a p-type third well diffusion layer; a p-type drain diffusion layer; a gate insulating film; a gate electrode; a device isolation insulating film; and a buffer layer. The buffer layer is formed between the first well diffusion layer and the third well diffusion layer to be in contact with an end of the third well diffusion layer opposing the source diffusion layer, and extends from immediately below the gate insulating film to a position deeper than a peak of curvature of impurity concentration distribution of the third well diffusion layer. The buffer layer has an impurity concentration lower than an impurity concentration in the third well diffusion layer.

Semiconductor device and method for manufacturing the same

An electrostatic protection element relating to the present invention comprises a P-type semiconductor and an N-type first impurity layer provided in the semiconductor substrate. The first impurity layer comprises a P-type second impurity layer functioning as a gate. The second impurity layer comprises an N-type third impurity layer functioning as a cathode. Further, the first impurity layer comprises an N-type fourth impurity layer spaced apart from the second impurity layer at a distance. The fourth impurity layer comprises a P-type fifth impurity layer functioning as an anode and an N-type sixth impurity layer. Then, in the electrostatic protection element, an impurity concentration of the fourth impurity layer is higher than that of the first impurity layer, and a bottom of the fourth impurity layer is deeper than that of the second impurity layer.

Electrostatic protection element

A semiconductor device includes an output pad and a surge absorption unit formed above a semiconductor region of a first conductivity type. The surge absorption unit includes: a semiconductor island region of a second conductivity type; a buried layer of the second conductivity type formed between a bottom of the semiconductor island region of the second conductivity type and the semiconductor region of the first conductivity type; a dopant layer of the first conductivity type formed in an upper portion of the semiconductor island region of the second conductivity type and connected to have the same potential as the semiconductor region of the first conductivity type; a dopant layer of the second conductivity type formed in an upper portion of the dopant layer of the first conductivity type and electrically connected to the output pad; and a ring layer of the second conductivity type surrounding the dopant layer of the first conductivity type and reaching the buried layer of the second conductivity type. In this device, the ring layer of the second conductivity type is electrically connected to a terminal with a fixed potential and contains a dopant of the second conductivity type having a higher concentration than the semiconductor island region of the second conductivity type.

Growing community of inventors

Osaka, Japan

Manabu Imahashi