Nec Electronics Corporation

Renesas Electronics Corporation

Nec Corporation

Manabu Iguchi

Toshiyuki Takewaki

Yoshihisa Matsubara

Daisuke Oshida

Toshiji Taiji

Yasuaki Tsuchiya

Masayuki Hiroi

Takuji Onuma

Masahiro Komuro

Mieko Hasegawa

Hironori Toyoshima

Hiroaki Nanba

Ichiro Honma

Takaharu Kunugi

Naoya Inoue

Ippei Kume

Mami Miyasaka

Akira Matumoto

Tadashi Fukase

Akira Matsumoto

Norio Okada

Takashi Ishigami

Makoto Sekine

Kazuyoshi Ueno

Kazuhiko Endo

Takuya Maruyama

Hiroyuki Kunishima

Kenichiro Hijioka

Makoto Ueki

Takahiro Onodera

Hiroki Shirai

Tetsuya Kurokawa

Ryuji Tomita

Hirokazu Katsuyama

The semiconductor device includes an insulating film that is formed using a cyclic siloxane having a six-membered ring structure as a raw material; a trench that is formed in the insulating film; and a interconnect that is configured by a metal film embedded in the trench. In the semiconductor device, a modified layer is formed on a bottom surface of the trench, in which the number of carbon atoms and/or the number of nitrogen atoms per unit volume is larger than that inside the insulating film.

Method of manufacturing semiconductor device

To provide a semiconductor device featuring reduced variation in capacitor characteristics. In the semiconductor device, a protective layer is provided at the periphery of the upper end portion of a recess (hole). This protective layer has a dielectric constant higher than that of an insulating layer placed in the same layer as the protective layer and configuring a multilayer wiring layer placed in a logic circuit region.

Semiconductor device with protective layer and method of manufacturing same

A semiconductor device includes a semiconductor substrate, and an insulating layer that is provided on the semiconductor substrate, wherein, in an internal circuit formation region of the insulating layer, a via hole and an interconnect trench, that is formed on the via hole and communicates with the via hole, are provided, in the via hole and the interconnect trench, a conductor is provided so as to integrally fill the via hole and said interconnect trench, in a dicing region of the insulating layer, a groove portion and an opening, that communicates with the groove portion and is formed to cover the groove portion when the semiconductor substrate is seen in plane view, are formed, and in the groove portion and the opening, a conductor is provided so as to integrally fill the groove portion and the opening.

Semiconductor device and method of manufacturing the same

A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.

A method of manufacturing a semiconductor device includes: forming a groove portion in a dicing region of an insulating layer and forming a via hole in an internal circuit formation region; providing a first resist film on the insulating layer; providing a second resist film to cover the first resist film; forming an interconnect opening in a region covering an internal circuit formation region of the second resist film and forming a position aligning opening in a region covering the dicing region of the second resist film; and detecting a positional relationship between the groove portion and the position aligning opening so as to detect whether the interconnect opening of the second resist film exists at a predetermined position with respect to the via hole of the insulating layer. In selective removing of the second resist film, the position aligning opening is formed such that a region of the position aligning opening covers the groove portion of the insulating layer.

Method of manfacturing semiconductor device

A semiconductor device having a structure which can be manufactured with a higher yield includes a local interconnection layer(a first interconnection layer) on a semiconductor substrateand a global interconnection layer(a second interconnection layer) on the local interconnection layerThe local interconnection layerand the global interconnection layerinclude a local interconnection(a first interconnection) and a global interconnection(a second interconnection), respectively, and the global interconnectionis thicker than the local interconnectionThe local interconnection layerand the global interconnection layeralso have a dummy interconnection(a first dummy interconnection) and a dummy interconnection(a second dummy interconnection), respectively. The dummy interconnectionis narrower than the dummy interconnection

Semiconductor device

A semiconductor device has a first guard ring surrounding a circuit region, a second ring disposed between the circuit region and the first guard ring, and first connections connecting the first guard ring and the second guard ring to each other. An area sandwiched between the first guard ring and the second guard ring is divided by the first connections into a plurality of subareas. Even if the first guard ring is partly defective, water enters from outside into only the subarea which is contiguous to the defective part of the first guard ring.

Semiconductor device with guard ring for preventing water from entering circuit region from outside

A method for manufacturing a semiconductor device comprises: forming an N region and P region on a substrate, forming wiring so as to connect one or both of these N and P regions; and performing a processing step on a semiconductor substrate on which the upper surface of said wiring is exposed using a liquid, wherein said processing step is performed in a state in which the wavelength of light radiated onto said semiconductor substrate is 500 nm to less than 1 &#x3bc;m, so that problems such as wiring connection defects for which there is the risk of occurring in the cleaning step are prevented by performing the cleaning step during, before or after a step that includes chemical mechanical polishing (CMP) for forming the above wiring.

Method for manufacturing semiconductor device, and processing system and semiconductor device

A semiconductor device having a multilayer interconnection structure includes a chip semiconductor substrate, a plurality of interlayer insulating layers disposed on the chip semiconductor substrate, a circuit section disposed on the chip semiconductor substrate, and a plurality of walls that extend through the interlayer insulating layers and are arranged along the peripheral portions of the chip semiconductor substrate such that the walls surround the circuit section. The walls include upper sub-walls and lower sub-walls. The upper sub-walls extend through one of the interlayer insulating layers and further extend into another one of the interlayer insulating layers disposed under the layer through which the upper sub-walls extend. The lower sub-walls extend through one of the interlayer insulating layers disposed under the layer through which the upper sub-walls extend. Lower portions of the upper sub-walls each extend into corresponding upper portions of the lower sub-walls.

Semiconductor device having multilayer interconnection structure and method for manufacturing the device

In a semiconductor device, a circuit unit is formed in an inside portion, and seal rings that enclose the inside portion that are composed of walls of metal layers are formed around the periphery. In the corners, the seal rings include linear parts that extend inwardly in addition to the linear parts that extend along the periphery, whereby the seal rings are formed in a planar pattern having small rectangular planar patterns in each corner.

Semiconductor device having superior resistance to moisture

A semiconductor apparatus includes an under layer, a first insulating layer and a first conductive portion. The under layer is formed above a substrate. The first insulating layer is formed on the under layer. The first conductive portion is formed in a first concave portion which passes through the first insulating layer to the under layer. The first conductive portion includes a first barrier metal layer and a first metal portion. The first barrier metal layer is formed on a side wall and a bottom surface of the first concave portion. The first metal portion is formed on the first barrier metal layer such that the rest of the first concave portion is filled with the first metal portion. The first metal portion includes a first alloy including copper and aluminium.

Semiconductor apparatus of which reliability of interconnections is improved and manufacturing method of the same

In the semiconductor device of the present invention, a plurality of dummy patterns are formed in a grid arrangement in the scribe line areas of a wafer, and a plurality of dummy patterns are formed in a diagonally forward skipped arrangement in the chip interior areas of the wafer. Altering the arrangement of dummy patterns in the chip interior areas and scribe line areas in this way enables formation of dummy patterns with greater uniformity in the chip interior areas and enables formation of dummy patterns with greater resistance to loss that occurs when dicing in scribe line areas.

Semiconductor device and method of fabricating semiconductor device with high CMP uniformity and resistance to loss that occurs in dicing

A semiconductor device having a plurality of interconnection layers includes signal lines formed of copper according to a single damascene process, vias formed of tungsten beneath the signal lines according to a single damascene process, and power and ground lines and vias therebeneath formed of copper according to a dual damascene process. Since copper has a better heat radiating capability than tungsten, the vias in all the layers have a better heat radiating capability than those formed of tungsten.

Growing community of inventors

Kanagawa, Japan

Manabu Iguchi