Hitachi, Ltd.

Hitachi Process Computer Engineering, Inc.

Other

Manabu Araoka

Tomoaki Nakamura

Yoshiaki Takahashi

Yoshihiro Miyazaki

Hiroaki Fukumaru

Nobuyasu Kanekawa

Masayuki Sakata

Yoshiki Kobayashi

Soichi Takaya

Shigenori Kaneko

Masayuki Tanji

Koji Masui

Takeshi Miyao

Saburou Iijima

Atsushi Shikama

Shinichiro Kanekawa

Katsunori Tagiri

Koji Ozawa

A computer system has a plurality of processing units (,-,-,-n) connected via one or more system buses (,-,-,). Each processing unit (,-,-,-n) has three or more processors (,-,-,-,) on a common support board (PL) and controlled by a common clock unit (,). The three processors (,-,-,-,) perform the same operation and a fault in a processor (,-,-,-,) is detected by comparison of the operations of the three processors (,-,-,-,). If one processor (,-,-,-,) fails, the operation can continue in the other two processors (,-,-,-,) of the processing unit (,-,-,-n), at least temporarily, before replacement of the entire processing unit (,-,-,-n). Furthermore, the processing unit (,-,-,-n) may have a plurality of clocks (A,B) within the clock unit (,), with a switching arrangement so that the processors (,-,-,-n) normally receive clock pulses from a main clock (A), but receive pulses from an auxiliary clock (B) if the main clock (A) fails. Switching between the main and auxiliary clock (A,B) involves comparison of the pulse duration from the clocks (A,B). Additionally, a plurality of cache memories (,) may be connected in common to the processors (,-,-,-,), so that failure of one cache memory (,) permits the processing unit (,-,-,-n) to continue to operate using the other cache memory (,). Coherence of the contents of the cache memories (,) may be achieved by direct comparison, and a comparison method can also be used to invalidate data in an internal cache memory (,-,-,-,) of a processor (,-,-,-,) which differs from that in the external cache memory (,). Coherence of protocols may also ensure that data in caches (,) of the different processor units (,-,-,-n) are always correct.

Processing unit for a computer and a computer system incorporating such a processing unit

A computer system has a plurality of processing units connected via one or more system buses. Each processing unit has three or more processors on a common support board (PL) and controlled by a common clock unit. The three processors perform the same operation and a fault in a processor is detected by comparison of the operations of the three processors. If one processor fails, the operation can continue in the other two processors of the processing unit, at least temporarily, before replacement of the entire processing unit. Furthermore, the processing unit may have a plurality of clocks (A,B) within the clock unit, with a switching arrangement so that the processors normally receive clock pulses from a main clock (A), but receive pulses from an auxiliary clock (B) if the main clock (A) fails. Switching between the main and auxiliary clock (A,B) involves comparison of the pulse duration from the clocks (A,B). Additionally, a plurality of cache memories may be connected in common to the processors, so that failure of one cache memory permits the processing unit to continue to operate using the other cache memory. Coherence of the contents of the cache memories may be achieved by direct comparison, and a comparison method can also be used to invalidate data in an internal cache memory of a processor which differs from that in the external cache memory. Coherence of protocols may also ensure that data in caches of the different processor units are always correct.

Processing unit for a computer and a computer system incorporating such

A multiple common memory system is provided in which at least three CPUs share at least two common memories each storing one and the same content. Each of the first and second CPUs contains a respective one of the two common memories, and each of the first and second CPUs has an arrangement to access the common memory therein at the time of requesting a read access to a common memory. Other CPUs in the system do not contain common memories, but do include arrangements to access the common memory of the first or second CPU at the time of requesting a read access to a common memory.

Method for controlling multiple common memories and multiple common

In a data processing device, when exchanging a plug-in package with another without breaking the power to be supplied to the data processing device, a package removing lever is equipped with a locking piece. The lever does not move and the package hence cannot be removed, until the locking piece is released. In response to the release operation of the locking piece, a switch is activated to break off the power supply for the package. After the package is mounted perfectly, the power for the package is switched on by the action of the locking piece, thus preventing any misoperation when removing the package.

Data processing device and plug-in package

In a data processing device, when exchanging a plug-in package with another without breaking off the power to be supplied to the data processing device, a package removing lever is equipped with a locking piece. The lever does not move and the package hence cannot be removed, until the locking piece is released. In response to the release operation of the locking piece, a switch is activated to break off the power supply for the package. After the package is mounted perfectly, the power for the package is switched on by the action of the locking piece, thus preventing any misoperation when removing the package.

An address translation circuit for translating a logical address into a physical address in a computer system using a virtual storage method includes two high-speed buffers (TLB's) for an instruction and an operand, respectively. One of the buffers is selected for use at the time of a memory access depending on a signal supplied from a processing unit to indicate whether the memory access is related to an instruction cycle or an operant cycle. This configuration enables a high-speed address translation without lowering the TLB hit rate and without increasing the amount of the hardware components.

Address translation circuit including two translation buffers

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Hitachi, Japan

Manabu Araoka