Nec Corporation

Hitachi-high-technologies Corporation

Hitachi High-tech Corporation

Ntt Docomo, Inc.

Nippon Electric Co., Ltd.

Manabu Ando

Akihisa Makino

Masahiko Iijima

Hajime Yamazaki

Keiko Yoshikawa

Shin Hasegawa

Tomonori Mimura

Sakuichiro Adachi

Kenji Kondou

Nolifumi Sato

Junji Monden

Hiroshi Furuta

Hironori Matsuda

A high-throughput automatic analyzer integrates a biochemical analysis section and a blood coagulation analysis section. The analyzer is capable of achieving a reduction in size, system cost, and lifecycle cost. The automatic analyzer includes: a reaction disk; a first reagent dispensing mechanism that dispenses a reagent to reaction cells on the reaction disk; a photometer that irradiates a reaction solution in the reaction cell with light; a reaction cell cleaning mechanism; a reaction vessel supply unit that supplies a disposable reaction vessel for mixing and reacting a sample and a reagent with each other; a second reagent dispensing mechanism that dispenses a reagent to the disposable reaction vessel; a blood coagulation time measuring section that irradiates a reaction solution in the disposable reaction vessel with light to detect transmitted or scattered light; and a sample dispensing mechanism that dispenses a sample to the reaction cell and the disposable reaction vessel.

Automatic analyzer

There is provided an automatic analyzer including: a sample pipetting mechanism, reagent pipetting mechanismsA andB, mixing mechanismsA andB, a scattered light photometer, and an absorption photometerall located on a transfer path of reaction cellsarranged circumferentially on a disk-shaped reaction disk, the reaction cellsbeing transferred in the circumferential direction by rotation of the reaction disk. Scattered light intensity and absorbance are controlled to be measured by causing the reaction cellsto move past a scattered light detection position and a transmitted light detection position in the same process of movement, the two positions being established beforehand on the transfer path. This makes it possible to suppress the effects on measurement results of the difference in time between scattered light measurement and absorbance measurement thereby improving measurement accuracy.

An automatic analyzer which can reduce the effort necessary for conducting a test of limit of detection/limit of quantification properties and managing the test results is provided. Operation condition-setting means for conducting an evaluation test for at least one of a limit of detection and a limit of quantification for each measurement item, determination condition-setting means for setting a determination condition of the evaluation test, and a calculation unit for obtaining a measurement result of a dilution series containing different dilution concentrations by controlling the sample-dispensing mechanism, the reagent-dispensing mechanism and the measurement unit based on the set operation condition, and calculating a test result of the evaluation test from the measurement result of the dilution series based on the set determination condition are disposed.

A mobile device comprises at least a program starter, a communication controller, a display controller, a display portion, and an instruction portion. The mobile device receives report information that is emitted in a predetermined period by a guidance information terminal upon entering the communication area of the guidance information terminal in a state where a guidance information display application has been started by the program starter. The mobile device causes the display portion to display a dialog screen for issuing an instruction with regard to whether to acquire guidance information by means of the display controller upon reception of the report information. When the acquisition of guidance information has been instructed by the instruction portion, the mobile device issues a request to the guidance information terminal to transmit the guidance information by means of the communication controller and receives the guidance information. The guidance information thus received is displayed on the display portion by means of the display controller.

Communication terminal, information supply system, and information supply method

A semiconductor memory device has a built-in error correction system for correcting undesirably inverted data bits, and the built-in error correction system starts a parity bit generating sequence and an error correcting sequence only when increase of error rate is forecasted, thereby increasing the access speed without sacrifice of the reliability.

Semiconductor memory device with error self-correction system starting

A flip-flop is composed of inverters including first and second MISFETs each comprising a TFT or an SOI transistor. A third MISFET, which comprises a TFT or an SOI transistor, has a gate connected to a write selecting signal line, and is connected between the output terminal of one of the inverters and a write/read signal line. A fourth MISFET has a gate connected to the gate of the other inverter. A fifth MISFET has a drain and a source connected to the write/read signal line and the drain of the fourth MISFET, and a gate connected to a read selecting signal line.

Semiconductor memory cell

A static memory device has memory cells each having a pair of driver MOSFETs, two load resistors each connected between a power source and a drain of each of the driver MOSFETs, two access MOSFETs each of which is connected between the drain of each of the driver MOSFETs and each of bit lines and gates of which are connected to a word line. In the memory cell, the thickness of a gate oxide film of the access MOSFET is made thicker than that of the gate oxide film of the driver MOSFET. The operation stability of the memory cell is enhanced, without the need of increasing a chip size, by increasing a ratio between the driver MOSFETs and the access MOSFETs of the memory cell (the ratio of current supplying capabilities of the two transistors) without making a gate size large or without making it so small as to cause process variations.

High stability static memory device having metal-oxide semiconductor

An asynchronous type static memory device in which a plurality of pairs of bit lines are equalized upon change of address signals at a high speed is disclosed. The memory device comprises a plurality of memory blocks having a plurality of pairs of bit lines and a plurality of equalizing circuits provided for the plurality of pairs of bit lines, a plurality of address terminals receiving address signals, and an address transistion detecting circuit having a plurality of detection units, each of the detection units being coupled to one of the address terminals and generating a detecting signal when the signal at the associated address terminal coupled thereto is changed, a first logic section for generating a first number of intermediate logic signals for performing logical sum with respect to outputs of the detection units, the first number being smaller than the number of the detection units, and a plurality of second logic sections provided for the plurality of memory blocks respectively, each of the second logic sections operatively generating a control signal for enabling the equalizing circuits associated therewith as a result of performing a logical sum of the intermediate logic signals.

Static memory device provided with a signal generating circuit for

A difference amplifier circuit comprises two series combinations coupled in parallel between a first source of voltage and a common node, an activation transistor responsive to a control signal for propagating a second voltage level to the common node and a channel conductance regulating circuit responsive to the control signal and operative to regulate channel conductances of the respective series combinations, so that the channel conductances are easily fallen within a target range through the function of the regulating circuit even if the process conditions are fluctuated.

Difference amplifier circuit

An output circuit protected by an abnormal voltage supplied at an output terminal is disclosed. The output circuit comprises a first switching circuit includes first and second transistors connected in series for providing an output terminal with a first potential therethrough in response to a first logic state of a logic signal, a second switching circuit for providing the output terminal with a second potential in response to a second logic state of the logic signal, and means for making the first and second transistors non-conducting when the first switching circuit is disenabled.

Tri-state output circuit provided with means for protecting against

A semiconductor memory device in which the selected word line is energized only during a limited period of time is disclosed. The memory device is equipped with a clock generator which generates a one-shot pulse signal in response to a change in address signal or to an application of a write-enable signal, and the selected word line is energized by the one-shot clock signal. The clock generator further generates a one-shot clock signal in response to a change in an input data signal in a data-write operation. The input data is thereby sorted into the accessed memory cell, even when the data to be stored is supplied a relatively long time after the write-enable signal is applied.

Semiconductor memory device with shortened time period of word line

A static semiconductor memory device includes a memory cell matrix having word and digit lines connected to memory cells, an X address decoder connected to the word lines, a gate circuit connected to the digit lines, a Y address decoder connected to a gate of the gate circuit, a sense amplifier connected to an output of the gate circuit, a latching circuit connected to an output of the sense amplifier, and an internal control circuit for supplying control signals to the above components. The internal control circuit controls so as to activate the X address decoder and the sense amplifier, precharge the latching circuit, supply a select signal representing an updated address to the selected word and digit lines, cause the latching circuit to latch a signal appearing across the digit line, and deactivate the X address decoder and the sense amplifier.

Growing community of inventors

Tokyo, Japan

Manabu Ando