Matsushita Electric Industrial Co., Ltd.

Mana Saishi

Shunichi Kurohmaru

Takayuki Minemaru

A multiplication method and a multiplication circuit, wherein a multiplicand is multiplied by a multiplier using a multiplication process, the result of the multiplication is added by an addition process to a rounding signal to be output from a rounding signal generation process, and the result of the addition, i.e., a multiplication result obtained after rounding, is stored in a register. By a barrel shifter, the multiplication result obtained after rounding stored in the register is shifted by a bit count indicated by a shift bit count signal. The shift bit count signal output from an instruction control process is input to the barrel shifter and a rounding signal generation process. The rounding signal generation process generates a rounding signal on the basis of the shift bit count signal indicating the bit count used to shift the multiplication result after rounding. By carrying out a rounding process in the addition process by using the rounding signal, the rounding process can be carried out at an appropriate position desired by the user without increasing instruction code or storage.

Multiplication method and multiplication circuit

A multiplication method and a multiplication circuit, wherein a multiplicand is multiplied by a multiplier by using a multiplication means, the result of the multiplication is added by an addition means to a rounding signal to be output from a rounding signal generation means, and the result of the addition, i.e., a multiplication result obtained after rounding, is stored in a register. By a barrel shifter, the multiplication result obtained after rounding stored in the register is shifted by a bit count indicated by a shift bit count signal. The shift bit count signal output from an instruction control means is input to the barrel shifter and a rounding signal generation means. The rounding signal generation means generates a rounding signal on the basis of the shift bit count signal indicating the bit count used to shift the multiplication result after rounding. By carrying out a rounding process in the addition means by using the rounding signal, the rounding process can be carried out at an appropriate position desired by the user.

A product P is calculated by multiplying a multiplicand X and a multiplier factor Y which are 16-bit fixed-point numbers and binary numbers in two's complement notation. Thus obtained product P is 31-bit length and the most significant bit thereof is a sign bit. Further, the product P is rounded down or rounded off to obtain a 16-bit rounded result PR. At this time, the 15-bit rounding data R to be added to the product P is changed according to the sign of the product P which is predicted so as to obtain respective rounded results which have the same absolute value from the two products which have different signs from each other and the same absolute value. In detail, in a case of rounding-down, '0000' and 'TFFF' (both in hexadecimal numeral) are respectively generated as the rounding data when the product P is positive and when the product P is negative. In a case of rounding-off, '4000' and '3FFF' (both in hexadecimal numeral) are respectively generated as the rounding data R when the product P is positive and when the product P is negative. The rounding data is added to the less significant 15 bits of the thus calculated product P and the less significant 15 bits of the thus added result are deleted to make the remaining 16 bits the rounded product PR.

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Fukuoka, Japan

Mana Saishi