Matsushita Electric Industrial Co., Ltd.

Mana Hamada

Masahiro Ohashi

Tomonori Yonezawa

Masayoshi Tojima

Masatoshi Matsuo

Shunichi Kuromaru

Shunichi Kurohmaru

Yuji Sugisawa

Miki Arita

Tsuyoshi Nakamura

Masayoshi Toujima

Yasuo Kouhashi

Masahiro Oohashi

An image decoding unit comprises a decoding unit, a data memory unit, a reconstruction unit, and a frame memory. The decoding unit includes an entropy decoder, a motion compensator, an inverse quantizer, and an inverse DCT unit. The data memory unit includes a data memory A and a data memory B. In the middle of the data transfer from the data memory unit to the frame memory, the reconstruction unit that inputs intermediate data of decoding and outputs reconstructed image data is provided; thereby, the processing of generating the reconstructed image data and the processing of storing the reconstructed image data into the frame memory can be performed in parallel. By the structure, a high-speed processing of image reconstruction can be performed.

Image decoding unit, image encoding/ decoding devices using image decoding unit, and method thereof

It is decided whether a first source data from the memoryis a data which is to be subjected to arithmetic or not by a state flag detection means, the result of the decision is retained as a state flag, and it is decided by a condition decision meanswhether or not the state flag satisfies a condition for performing the arithmetic. A control meanscontrols whether an ALUshould perform the arithmetic or not on the basis of the condition satisfaction/dissatisfaction information.

Conditional vector arithmetic method and conditional vector arithmetic unit

A system which allows signal transmission between circuit blocks is constructed promptly by automatically generating an I/F circuit in response to the adjustment of a timing relationship and to a modification in a waveform on a GUI and automatically inserting the I/F circuit between the circuit blocks or adding the I/F circuit to any of the circuit block. A circuit for outputting an operation enable for a receiving side is generated automatically between a plurality of blocks operating with different frequencies, whereby the use of the circuit blocks is expanded in spite of the different frequencies. Further, the design of a large-scale system is performed efficiently by automatically generating a desired waveform by a simple editing operation, generating a desired signal waveform by forming a combinational circuit of signals in the circuit block, and automatically generating a logic synthesis script.

Method of designing semiconductor integrated circuit device

An image processing apparatus according to the present invention comprises a general arithmetic circuit comprising a program control circuit , a first address generator , a first data memory , a first pipeline operation circuit , a second address generator , a second data memory and a second pipeline operation circuit , and a dedicated arithmetic circuit comprising a control circuit , a first dedicated pipeline operation circuit , a second dedicated pipeline operation circuit , . . . , an N-th dedicated pipeline operation circuit , as shown in FIG. The arithmetic unit having the above-described structure, for example, can realize an arithmetic unit which can be applied to various applications. Further, considering the age of IP (Intellectual Property) which will come in the future, the arithmetic unit can exhibit the flexibility toward the applications.

Processor and image processing device

A high-function address generating apparatus is realized which generates a memory address that can access a multidimensional area without running over a memory area specified by a user. Continuous addressing domain which is determined by a top address and a final address is set by an addressing domain setting means , an address is generated by a two-dimensional address generating means , the address in a two-dimensional area is compared with the final address and the top address by a first and a second comparing means and , respectively, whether it runs over the addressing domain or not is judged by an address correction means , and an address running over is corrected so as to not run over.

Address generating apparatus and motion vector detector

A system which allows signal transmission between circuit locks is constructed promptly by automatically generating an I/F circuit in response to the adjustment of a timing relationship and to a modification in a waveform on a GUI and automatically inserting the I/F circuit between the circuit blocks or adding the I/F circuit to any of the circuit block. A circuit for outputting an operation enable for a receiving side is generated automatically between a plurality of blocks operating with different frequencies, whereby the use of the circuit blocks is expanded in spite of the different frequencies. Further, the design of a large-scale system is performed efficiently by automatically generating a desired waveform by a simple editing operation, generating a desired signal waveform by forming a combinational circuit of signals in the circuit block, and automatically generating a logic synthesis script.

For every data, the number of data matches that occurred consecutively is written to a memory together with nonmatching data, and data from the memory is read out to continuously perform subsequent data processing and detect, at the same time, the last data written to the memory. To achieve this, a desired value is set in a data register, and a comparison instruction is issued by which the value set in the register is compared with a value set in a second register, and the number of matches that occurred consecutively is output together with nonmatching data; upon the output of a retrieval counter reaching a predetermined value, the comparison instruction is terminated, whereupon the number of consecutive matches, the nonmatching data, and an end flag signal are written to the memory at the same address.

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Fukuoka, Japan

Mana Hamada