Samsung Electronics Co., Ltd.

Man-Sug Kang

Jae-young Ahn

Young-Seok Kim

Jae-Duk Lee

Jeong-Hee Park

Byoung-Deog Choi

Yong-Woo Hyung

Jin-ho Oh

Bong-Hyun Kim

Jung-Hwan Kim

Hideki Horii

Hee-Sook Park

Jin-Gyun Kim

Hye-Young Park

Dong-Ho Ahn

Jae-Hwa Park

Doo-Hwan Park

Tae-Han Kim

Gyu-Hwan Oh

Hong-suk Kim

Hyo-Jung Kim

Bong-hyun Kim

Young-kuk Kim

Woo-Sung Lee

Hyun-Jin Shin

Jung-hwan Park

Woong-Hee Sohn

Seung-Mok Shin

Jai-Dong Lee

Hee-Seok Kim

Won-Seok Yoo

Sang-Ryol Yang

Yong-Sun Lee

Keum-Joo Lee

Ju-Wan Lim

Sung-Hae Lee

Jae-Young Ahn

Jin-Tae No

Hyoung-Jo Huh

A semiconductor device includes a gate trench across an active region of a semiconductor substrate, a gate structure filling the gate trench, and source/drain regions formed in the active region at respective sides of the gate structure. The gate structure includes a sequentially stacked gate electrode and insulating capping pattern, and a gate dielectric layer between the gate electrode and the active region. The gate electrode is located at a lower level than an upper surface of the active region and includes a barrier conductive pattern and a gate conductive pattern. The gate conductive pattern includes a first part having a first width and a second part having a second width greater than the first width. The barrier conductive pattern is interposed between the first part of the gate conductive pattern and the gate dielectric layer.

Semiconductor device

Methods of manufacturing non-volatile memory devices may include separating first phase-change material groups and second phase-change material groups, which have different sizes, from a target including phase-change materials and faulting a phase-change material layer on an object by using the first phase-change material groups and the second phase-change material groups.

Methods of manufacturing non-volatile phase-change memory devices

An example embodiment relates to a method including forming a bottom electrode and an insulating layer on a substrate, the insulating layer defining a first opening that exposes a portion of the bottom electrode. The method includes forming a variable resistance material pattern, including a plurality of elements, to fill the first opening. The variable resistance material pattern may be doped with a dopant that includes at least one of the plurality of elements in the variable resistance material pattern. The method includes forming a top electrode on the variable resistance material pattern.

Method of manufacturing variable resistance memory device

A phase change structure includes a first phase change material layer pattern and a second phase change material layer pattern. The first phase change material layer pattern may partially fill a minute structure, and the second phase change material layer pattern may fully fill the minute structure. The first phase change material layer pattern may include a first phase change material, and the second phase change material layer pattern may include a second phase change material having a composition substantially different from a composition of the first phase change material.

Methods of forming a phase change layer and methods of fabricating a phase change memory device including the same

Example embodiments relate to a method of manufacturing a capacitor and a method of manufacturing a semiconductor device using the same. Other example embodiments relate to a method of manufacturing a capacitor having improved characteristics and a method of manufacturing a semiconductor device using the same. In a method of manufacturing a capacitor having improved characteristics, an insulation layer, including a pad therein, may be formed on a substrate. An etch stop layer may be formed on the insulation layer. A mold layer may be formed on the etch stop layer. The mold layer may be partially etched by a first etching process to form a first contact hole exposing the etch stop layer. The mold layer may be partially etched by a second etching process to form a second contact hole. The exposed etch stop layer may be etched by a third etching process to form a third contact hole exposing the pad. A native oxide layer on the exposed pad may be removed by a fourth etching process to form a capacitor contact hole. A conductive layer may be formed in the capacitor contact hole to form a capacitor.

Method of manufacturing a capacitor and method of manufacturing a semiconductor device using the same

Example embodiments of the present invention relate to methods of manufacturing a semiconductor device. Other example embodiments of the present invention relate to methods of manufacturing a semiconductor device having a gate electrode. In the method of manufacturing the semiconductor device, a gate electrode may be formed on a semiconductor substrate. Damage in the semiconductor substrate and a sidewall of the gate electrode may be cured, or repaired, by a radical re-oxidation process to form an oxide layer on the semiconductor substrate and the gate electrode. The radical re-oxidation process may be performed by providing a nitrogen gas onto the semiconductor substrate while increasing a temperature of the semiconductor substrate to a first temperature to passivate a surface of the gate electrode under a nitrogen gas atmosphere, providing an oxygen gas onto the semiconductor substrate while increasing the temperature from a first temperature to a second temperature to perform a first oxidation process and/or performing a second oxidation process at the second temperature.

Methods of manufacturing a semiconductor device

A method for forming a low-k dielectric layer for a semiconductor device using an ALD process including (a) forming predetermined interconnection patterns on a semiconductor substrate, (b) supplying a first and a second reactive material to a chamber having the substrate therein, thereby adsorbing the first and second reactive materials on a surface of the substrate, (c) supplying a first gas to the chamber to purge the first and second reactive materials that remain unreacted, (d) supplying a third reactive material to the chamber, thereby causing a reaction between the first and second materials and the third reactive material to form a monolayer, (e) supplying a second gas to the chamber to purge the third reactive material that remains unreacted in the chamber and a byproduct; and (f) repeating (b) through (e) a predetermined number of times to form a SiBN ternary layer having a predetermined thickness on the substrate.

Method for forming a low-k dielectric layer for a semiconductor device

A semiconductor device and method of production are disclosed, the method including forming a preliminary gate electrode on a semiconductor substrate, the preliminary gate electrode including a gate oxide layer pattern and a conductive layer pattern stacked on the gate oxide layer pattern, and performing a re-oxidation process for curing damage of the semiconductor substrate and/or a sidewall of the conductive layer pattern, when the preliminary gate electrode is formed by forming an oxide layer on an outer surface of the preliminary gate electrode and on the semiconductor substrate, by supplying an oxygen gas and a chlorine-including gas while restraining a thickness of the gate oxide layer pattern from being increased; and the semiconductor device comprising a preliminary gate electrode formed on a semiconductor substrate, the preliminary gate electrode including a gate oxide layer pattern and a conductive layer pattern stacked on the gate oxide layer pattern, and a re-oxidized semiconductor substrate and/or a sidewall of the conductive layer pattern, with damage cured therein by supplying an oxygen gas and a chlorine-including gas while restraining a thickness of the gate oxide layer pattern from being increased.

Method for forming a gate electrode in a semiconductor device including re-oxidation for restraining the thickness of the gate oxide

Insulating layers in semiconductor devices having a multi-layer nanolaminate structure of SiNx thin film and BN thin film and methods for forming the same

A semiconductor memory device having a floating gate and a method of manufacturing the same, where a conductive layer for a floating gate is deposited on a semiconductor substrate and etched to form a conductive layer pattern. An annealing of the semiconductor substrate is carried out in an ambient atmosphere of hydrogen gas. Alternatively, an entire surface of the conductive layer pattern is etched by a dry etching method or a wet etching method. As a result, at least one edge of the conductive layer pattern is rounded, which reduces the likelihood that an electric field is concentrated at the edge and reduces a likelihood that the dielectric layer formed on the floating gate is thinner at the edge.

Method of making semiconductor memory device having a floating gate with a rounded edge

Method for forming a gate electrode in a semiconductor device

Growing community of inventors

Suwon-si, South Korea

Man-Sug Kang