Gte Automatic Electric Laboratories Incorporated

Gte Lenkurt Incorporated

Cirrus Logic Inc.

Gte Communication Systems Corporation

Gte Automatic Electric Incorporated

Acumos, Inc.

Man S Lee

Chieh Chang

Alex Lushtak

The 'chip set' of a graphics adapter interface card is reduced to a monolithic integrated circuit that includes a programmable analog clock circuit for producing a video memory clock and a video dot clock. A digital graphics adapter controller is responsive to the video memory clock and the video dot clock to produce a video information stream. A random-access memory is responsive to the video information stream to produce a video display information stream, and a digital-to-analog converter is responsive to the video display information stream to convert the video display information stream to analog signals for application to a video display device.

VGA controller circuitry

An M of N decoder circuit includes N output terminals, log.sub.2 (n+1) logic input terminals, two voltage input terminals, and (N+1)log.sub.2 (N+1) pass transistors, each having a gate connected to one of the logic input terminals, a source connected to one of a voltage input terminal and an output terminal, and a drain connected to one of said output terminals, each of the pass transistors for passing a voltage signal from source to drain when the gate has applied to it one logic level and for not passing said voltage signal when the gate has applied to a different logic level. More particularly, half of the pass transistors are of one conduction type and half of the pass transistors are of an opposite conduction type. The gates of N+1 pass transistors are connected to each of the log.sub.2 (M+1) input terminals. For i =0 to log.sub.2 (N+1)-1, pass transistors of one conduction type whose gates are connected to an i-th input terminal are connected in groups of 2.sup.i, and pass transistors of the opposite conduction type whose gates are connect to the i-th input terminal are also connected in groups of 2.sup.i.

Compact glitchless M of N decoder circuit for digital to analog

A CMOS circuit for steering current utilizing minimal power includes a first stage comprising a first powering transistor and a first idling transistor essentially in a parallel configuration and placed in series with a second stage comprising a second powering transistor and a second idling transistor also essentially in a parallel configuration. The circuit is configured to allow the first idling transistor to supply a substantially constant low level, idling current, and the first powering transistor to controllably supply a higher, powering current. The second stage serves to direct the electric current provided by the first stage. When powering current is not required, the circuit draws only the low idling current.

CMOS current steering circuit

An integrated single-sideband modulator comprises six integrated capacitors C1-C6 and first switch means alternately connecting C1 and C2 as feedback capacitors across a differential input operational amplifier A1. The amplifier has a virtual ground potential on its inverting input terminal for causing it to operate as a voltage source and render the circuit relatively insensitive to parasitic capacitance effects associated with capacitor plates. Second switch means cooperates with A1, C1 and C2 and is responsive to 4-phase clock signals for driving input capacitors C3-C6 so as to convert first and second quadrature-phase input signal voltages into first and second electrical charge flow signals on the inverting input terminal that are a function of products of representations of the first and second voltages in switch state time intervals and associated pulse trains which have a 90.degree. phase difference therebetween and a repetitive pattern such as +1, +1, -1, -1, etc. The amplifier and feedback capacitors combine the charge signals for producing a single-sideband signal on A1's output terminal. This circuit is converted to a balanced modulator by omitting C5 and C6. In an alternate embodiment of a single sideband modulator that requires only a pair of switched capacitors C11 and C12, a 4-phase switch means alternately charges C11 and C12 with associated ones of the quadrature-phase input signal voltages while alternately connecting C12 and C11 as feedback capacitors across A1, the polarity of each capacitors feedback voltage being reversed each time that capacitor is connected across the amplifier. This circuit is operated as a balanced modulator by omitting one of the capacitors.

Switched capacitor DSB modulator/demodulator

Switched capacitor SSB modulator

A first embodiment of an integrable switched capacitor modulator comprises a differential input operational amplifier A1 having a virtual ground potential impressed on its inverting input terminal; capacitors C1, C2 and C3; and switch means operative for alternately (1) charging C1 with an input voltage while connecting C2 and C3 in series with A1 and across it, respectively, for causing it to produce an inverted version of the input voltage, and (2) discharging C2 and C3 while connecting the sample of the input voltage on C1 across A1 for causing it to output a non-inverted sample of the input voltage. The modulated output signal from A1 is preferably bandpass filtered to eliminate baseband spectral components fed through A1 when C2 is connected in series with the input terminal thereof. In a second embodiment which is insensitive to feedthrough and which requires only two capacitors C1 and C4, the switch means alternately (1) charges C1 with the input voltage while connecting a prior sample of the input voltage on C4 across A1 for causing it to output an inverted sample of the input voltage, and (2) charges C4 with the input signal while connecting the sample of the input voltage on C1across A1 in the opposite polarity for causing it to output a non-inverted sample of the input voltage. This embodiment has particular advantage as a demodulator since the built-in sample-and-hold function provides low pass filtering of the output signal of A1.

Switched capacitor AM modulator/demodulator

A first embodiment of an integrable switched capacitor modulator comprises a differential input operational amplifier A1 having a virtual ground potential impressed on its inverting input terminal; capacitors C1, C2 and C3; and switch means operative for alternately (1) charging C1 with an input voltage while connecting C2 and C3 in series with A1 and across it, respectively, for causing it to produce an inverted version of the input voltage, and (2) discharging C2 and C3 while connecting the sample of the input voltage on C1 across A1 for causing it to output a non-inverted sample of the input voltage. The modulated output signal from A1 is preferrably bandpass filtered to eliminate baseband spectral components fed through A1 when C2 is connected in series with the input terminal thereof. In a second embodiment which is insensitive to feedthrough and which requires only two capacitors C1 and C4, the switch means alternately (1) charges C1 with the input voltage while connecting a prior sample of the input voltage on C4 across A1 for causing it to output an inverted sample of the input voltage, and (2) changes C4 with the input signal while connecting the sample of the input voltage on C1 across A1 in the opposite polarity for causing it to output a non-inverted sample of the input voltage. This embodiment has particular advantage as a demodulator since the built-in sample-and-hold function provides low pass filtering of the output signal of A1.

An integrated single-sideband modulator comprises six integrated capacitors C1-C6 and first switch means alternately connecting C1 and C2 as feedback capacitors across a differential input operational amplifier A1. The amplifier has a virtual ground potential on its inverting input terminal for causing it to operate as a voltage source and render the circuit relatively insensitive to parasitic capacitance effects associated with capacitor plates. Second switch means cooperates with A1, C1 and C2 and is responsive to 4-phase clock signals for driving input capacitors C3-C6 so as to convert first and second quadrature-phase input signal voltages into first and second electrical charge flow signals on the inverting input terminal that are a function of products of representations of the first and second voltages in switch state time intervals and associated pulse trains which have a 90.degree. phase difference therebetween and a repetitive pattern such as +1, +1, -1, -1, etc. The amplifier and feedback capacitors combine the charge signals for producing a single-sideband signal on A1's output terminal. This circuit is converted to a balanced modulator by omitting C5 and C6. In an alternate embodiment of a single sidebank modulator that requires only a pair of switched capacitors C11 and C12, a 4-phase switch means alternately charges C11 and C12 with associated ones of the quadrature-phase input signal voltages while alternately connecting C12 and C11 as feedback capacitors across A1, the polarity of each capacitor's feedback voltage being reversed each time that capacitor is connected across the amplifier. This circuit is operated as a balanced modulator by omitting one of the capacitors.

Switched capacitor balanced modulator/demodulator

A switched capacitor N-path filter in which all capacitors that introduce delay in the paths, in that they have memory and are characterized such that the new charge flow into each such capacitor during each commutation cycle depends on the old charge on it from the previous commutation cycle, are replaced with an associated plurality of N-commutating capacitors.

Switched capacitor n-path filter

A circuit for simulating the parallel combination of a floating inductor and capacitor in the bilinear and LDI domains has a pair of nodes receiving an input voltage and connected to input terminals of associated first and second voltage followers. A first capacitor C1 is alternately or periodically connected across the output terminals of the voltage followers for sampling the input voltage, and connected between the output of the second voltage follower and the input terminal of an integrator including a second capacitor C2 which integrates and stores the charge voltage on C1. A third capacitor is periodically connected to the nodes for sampling the input voltage, and connected between the output terminals of the first voltage follower and the integrator for subsequently also sampling and storing the integrated voltage on C2. The sum of the input voltage and the integrated voltage that is stored by C3 is discharged to the new input voltage when C3 is again connected across the nodes. The parallel combination of a grounded inductor and capacitor is simulated by replacing one of the voltage followers with a short circuit and connecting the associated node to ground. An inductor alone is simulated across the nodes by proper selection of values of the three capacitors.

Simulation circuit employing switched capacitors

An integratable circuit that simulates a source resistor comprises first and second nodes for connection to a voltage source and a virtual ground, respectively; a first integrated capacitor C1; and switch means operative for alternately electrically connecting C1's top and bottom plates to the first node and ground, respectively, and to ground and the second node, respectively, during first and second non-overlapping time periods in each time interval T for charging C1 to the source voltage and discharging C1 into the second node, respectively, where T is the time interval between adjacent second time periods and f=1/T is the switching frequency for C1. The switch means also operates for making similar connections to plates of second and third capacitors C2 and C3 in different time periods of ones of successive time intervals T, both C2 and C3 sampling a source voltage in synchronism with sampling by C1 during adjacent time intervals and holding a charge voltage for a time interval T prior to being discharged into the second node. The circuit simulates a source resistor when the first node is electrically connected to the output terminal of a voltage source that is connected to ground. This circuit configuration simulates a bilinear source resistor when the capacitances are the same values and the circuit is characterized by the bilinear transformation.

Switched-capacitor source resistor simulation circuit

An integrated circuit comprising first and second nodes that are connected to external circuitry, a voltage follower having input and output terminals electrically connected between the second node and the bottom plate of a first integrated capacitor C1, and second and third integrated capacitors C2 and C3 having the bottom plates thereof connected to a ground reference potential. A switch means is operative for periodically electrically connecting the top plate of C1 to the first and second nodes during first and second non-overlapping time periods in each time interval T for discharging C1 and charging C1 to the difference voltage across the nodes, respectively, where T is the time interval between adjacent second time periods and f=1/T is the switching frequency for C1. The switch means also operates for periodically electrically connecting the top plates of C2 and C3 to the second and first nodes. The circuit simulates a source resistor when the first node is electrically connected to the output terminal of a voltage source that is connected to ground. This circuit configuration simulates a bilinear source resistor when the capacitances of C1, C2 and C3 are the same values, and the circuit is characterized by the bilinear transformation.

This simulation circuit is a one-port network having a pair of nodes connected to inputs of first and second voltage followers that have associated switched capacitors alternately connected across them for being discharged and connected to an integrator for being charged to the output voltage on the latter. A third switched capacitor is alternately connected in series with the voltage follower outputs for sensing the input voltage applied to the nodes, and connected to the integrator where the input voltage is integrated and transferred to the first and second switched capacitors. A floating inductance L=T.sup.2 C4/C1C3 is simulated across the nodes, where T is the reciprocal of the switching frequency, C1, C2 and C3 are the capacitances of associated switched capacitors, C1=C2, C4 is the capacitance in the integrator, and the circuit is characterized by the LDI transformation.

Switched-capacitor floating-inductor simulation circuit

An integratable switched capacitor simulation circuit comprising an integrated capacitor C3 having bottom and top plates thereof electrically connected to first and second nodes, and a pair of integrated capacitors C1 and C2 having their top plates electrically connected together. The bottom plate of C2 is electrically connected to the output of a voltage follower that has its input terminal connected to the second node. A first switch means periodically connects the top plates of C1 and C2 to the first and second nodes at a prescribed rate. When the first node is connected to a voltage source and the bottom plate of C1 is connected to either ground or the first node, the circuit simulates a source resistor across the nodes. When the first node and bottom plate of C1 are connected to ground, the circuit simulates a grounded resistor. In alternate embodiments, the capacitances of C1 and/or C3 may be zero valued for presenting an open circuit across the terminals thereof. In yet another embodiment where C1 and C3 are zero valued and the first node is connected to ground, a second switch means essentially operating 180.degree. out of phase with respect to the first switch means is located in the electrical connection of the bottom plate of C2 and the output terminal of the voltage follower for periodically connecting the bottom plate of C2 to the first node and the output of the voltage follower for causing the circuit to simulate a bilinear grounded resistor. In an alternate embodiment of this structure, the first node is connected to the output of a voltage source for simulating a bilinear source resistor.

Growing community of inventors

San Mateo, CA, United States of America

Man S Lee