International Business Machines Corporation

Man M Bui

Andrew S Potemski

A phase lock detector circuit for detecting the lock state of a phase locked loop (PLL) such that it is known when a synthesized clock has achieved a stable phase relationship with its reference clock signal. The PLL includes an input for receiving the reference signal, a digital phase detector, a voltage controlled oscillator, and a frequency divider. The phase lock detector of the present invention includes a loss of lock detector (LOLD) connected to the frequency divider, the phase detector and the input. The LOLD detects the occurrence of a selected phase difference between the reference signal and an output of the frequency divider for a selected number of cycles. Also included is a gain of lock detector (GOLD) connected to the frequency divider and the input. The GOLD detects the occurrence of the reference signal within a selected phase difference of an output of the frequency divider for a second selected number of cycles. The outputs of the LOLD and the GOLD are connected to a latch for generating a composite signal responsive to signals generated by the LOLD and the GOLD such that the composite signal has a first state indicating when the PLL is in a locked condition and a second state indicating when the PLL is in an unlocked condition. The phase differences and the selected number of cycles of the LOLD and GOLD may be programmed, as desired.

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Playa del Rey, CA, United States of America

Man M Bui