Sandisk Technologies Inc.

Sandisk Corporation

Western Digital Technologies, Inc.

Sandisk Tehcnologies Inc.

Man Lung Mui

Seungpil Lee

Yingda Dong

Hao Nguyen

Chris Avila

Gautam Ashok Dusija

Masaaki Higashitani

Xiying Costa

Deepak Raghu

Nima Mokhlesi

Pao-Ling Koh

Alexander Kwok-Tung Mak

Deepak Chandra Sekar

Haibo Li

Chris Nga Yee Avila

Ken Oowada

Jongmin Park

Juan Lee

Jian Feng Chen

Mohan Dunga

Teruhiko Kamei

Tien-Chien Kuo

Khanh Vinh Nguyen

Fanglin Zhang

Alex Mak

Prashanti Govindu

Johann Alsmeier

Gerrit Jan Hemink

Hock C So

Cynthia Hsu

Chi-Ming Wang

Shahzad Khalid

Kenneth Louie

Kwang Ho Kim

Deepanshu Dutta

Yupin K Fong

Jun Wan

Siu Lung Chan

Hitoshi Miwa

Yosuke Kato

Toru Ishigaki

Yee Lih Koh

Wendy Ou

Jong Park

Roy E Scheuerlein

Yan Li

Alon Marcu

Toru Miwa

Yacov Duzly

YenLung Li

Fumitoshi Ito

Manabu Sakai

Amul Dhirajbhai Desai

Seung Yu

Yuval Kenan

Christopher John Petti

James K Kai

Jeffrey W Lutze

Feng Q Pan

Tong Zhang

Henry Chien

Dengtao Zhao

Fumiaki Toyama

Daniel Edward Tuers

Wei Zhao

Grishma Shah

Changyuan Chen

Tai-Yuan Tseng

Sahil Sharma

Mrinal Kochar

Eran Erez

Yuki Mizutani

Zhenyu Lu

Shinji Sato

Ohwon Kwon

Yongke Sun

Dmitry Vaysman

Sung-En Wang

Trung Pham

Yichao Huang

James B Hart

Kou Tei

Oleg Kragel

Tapan Samaddar

Wenguang Shi

Vijay Sivasankaran

Alexander Chu

Masahide Matsumoto

Jiyin Xu

Chia-Lin Hsiung

Xiaolong Hu

Koji Miyata

Khanh T Nguyen

Alexander Tsang-Nam Chu

Han Chen

Alexander Kwog-Tung Mak

Eakta Anchila

Vamsi Krishna Sakhamuri

Binh Lee

Gyuwan Kwon

Embodiments described herein provide a linked XOR flash data protection scheme for data storage devices. In particular, the embodiments described herein provide a data storage controller with a memory space efficient XOR-based flash data protection/recovery algorithm with minimal flash block space overhead and support of recovery from full plane failure with neighbor planes disturb (NPD) in a single word line. Additionally, the embodiments described herein provide a reduced flash block space dedicated for XOR parity buffers storage by a factor of a number of planes per die without losing the capability to recover from NPD.

Linked XOR flash data protection scheme

The present disclosure generally relates to thermal throttling a nonvolatile memory device in a data storage device. Nonvolatile memory devices can sustain higher temperatures for a limited duration of time as part of the lifecycle/operation of the device. By allowing for a small margin of time at a higher temperature of operation, the maximum capability of the data storage device is increased. In so doing, the data storage device reliability can be maintained while increasing the device performance.

SSD operation in a nonoptimal memory environment

The present disclosure describes a system, a circuit, and method for process and temperature compensation in an integrated circuit. For example, the system includes a bus, a data latch, and a voltage generator. The data latch includes a plurality of transistors coupled to the bus. The voltage generator includes a tracking transistor with one or more physical characteristics that substantially match one or more respective physical characteristics&#x2014;e.g., gate width and gate length dimensions&#x2014;of at least one of the plurality of transistors in the data latch. The voltage generator is configured to adjust a pre-charged voltage on the bus based on an electrical characteristic of the tracking transistor.

Voltage generator to compensate for process corner and temperature variations

Techniques are presented for the programming of a non-volatile memory in which multi-state memory cells use a charge trapping layer. When writing data onto a word lines, different data states are written individually, while programming inhibiting the other states, thereby breaking down the write operation into a number of sub-operations, one for each state to be written. This allows for improved timing and decreased power consumption.

Programming techniques for non-volatile memories with charge trapping layers

In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages, a structure and corresponding for efficiently programming of such select gates. On the drain side, the end most of multiple drain select transistors is individually controllable and used for biasing purposes while one or more other drain side select gates are collectively programmed to set adjust their threshold voltage. Independently, on the source side, the end most of multiple source select transistors is individually controllable and used for biasing purposes while other source side select gates are collectively programmed to set adjust their threshold voltage.

Techniques for programming of select gates in NAND memory

In non-volatile memory circuits, the amount of time needed for bit lines to settle can vary significantly depending on the location of the blocks selected. For example, in a sensing operation, the amount of time for bit lines to settle when being pre-charged by sense amplifiers will be shorter for blocks near the sense amps than for far side blocks. These variations can be particularly acute in high density memory structures, such as in 3D NAND memory, such as that of the BiCS variety. Rather than use the same timing for all blocks, the blocks can be segmented into groups based on their proximity to the sense amps. When performing a sensing operation, the timing can be adjusted based on the block group to which a selected page of memory cells belongs.

Segmentation of blocks for faster bit line settling/recovery in non-volatile memory devices

Techniques are provided for efficiently performing programming operations in a memory device. In particular, power consumption is reduced in sensing circuitry by avoiding pre-charging of bit lines for certain memory cells at certain times during a programming operation. One approach uses knowledge of the different phases of a programming operation to reduce the number of unnecessary bit line pre-charges. For example, during the lower program loop numbers of a programming operation, bit line pre-charging may occur for lower data states but not for higher data states. Similarly, during the higher program loop numbers, bit line pre-charging may occur for higher data states but not for lower data states. In another approach, which may or may not incorporate knowledge of the different phases of a programming operation, the setting of the bit line pre-charge can be updated at least once after it is initially set in the verify portion.

Adaptive selective bit line pre-charge for current savings and fast programming

In NAND Flash memory, bit line precharge/discharge times can be a main component in determining program, erase and read performance. In a conventional arrangement bit line levels are set by the sense amps and bit lines are discharged to a source line level is through the sense amplifier path. Under this arrangement, precharge/discharge times are dominated by the far-side (relative to the sense amps) based on the bit lines' RC constant. Reduction of bit line precharge/discharge times, therefore, improves NAND Flash performance and subsequently the overall system performance. To addresses this, an additional path is introduced between bit lines to the common source level through the use of dummy NAND strings. In an exemplary 3D-NAND (BiCS) based embodiment, the dummy NAND strings are taken from dummy blocks, where the dummy blocks can be placed throughout the array to evenly distribute the discharging current.

Utilizing NAND strings in dummy blocks for faster bit line precharge

A compact and versatile high speed sense amplifier suitable for use in non-volatile memory circuits is presented. The sense amp circuit is connected to first and second supply levels, a first level used for setting a program inhibit level on bit lines and a second level used for pre-charging bit lines for sensing operation. Outside of a data latch, the sense amp can employ only NMOS transistors. The arrangement of the circuit also allows for the discharging the bit line at the same time as transfers the sensing result out to other latches.

Compact high speed sense amplifier for non-volatile memory with reduced layout area and power consumption

A non-volatile memory includes an data latch structure for programming bit lines using at least three programming levels. A sense amplifier includes a first data latch for controlling the voltage of a corresponding bit line, and a second static data latch with scan circuitry for performing logic operations on the program data and sense results. The sense amplifier scans low verify sense results with program data to generate reduced programming data. The reduced programming data is transferred out of the first data latch after sensing for all states and the program data is scanned to generate program enable/inhibit data which is stored in the first data latch. After setting the bit line to a program inhibit or program enable level, the reduced programming data is transferred back to the first data latch. The bit lines for reduced programming are then adjusted to the reduced programming level.

Sense amplifier with efficient use of data latches

A multi-tier memory device is formed over a substrate such that memory stack structures extend through an alternating stack of insulating layers and electrically conductive layers within each tier. Bit lines are formed between an underlying tier having drain regions over semiconductor channels and an overlying tier having drain regions under semiconductor channel, such that the bit lines are shared between the underlying tier and the overlying tier. Source lines can be formed over each tier in which source regions overlie semiconductor channels and drain regions. If another tier is present above the source lines, the source lines can be shared between two vertically neighboring tiers.

Multi tier three-dimensional memory devices including vertically shared bit lines

A non-volatile memory system that has two or more sub-blocks in a block performs a check before accessing memory cells to see if the condition of a sub-block that is not being accessed could affect the memory cells being accessed. If such a sub-block is found then parameters used to access the cells may be modified according to a predetermined scheme.

Compensation for sub-block erase

Programming techniques for a three-dimensional stacked memory device provide compensation for different intrinsic programming speeds of different groups of memory cells based on the groups' locations relative to the edge of a word line layer. A larger distance from the edge is associated with a faster programming speed. In one approach, the programming speeds are equalized by elevating a bit line voltage for the faster programming memory cells. Offset verify voltages which trigger a slow programming mode by elevating the bit line voltage can also be set based on the group locations. A programming speed can be measured during programming for a row or other group of cells to set the bit line voltage and/or the offset verify voltages. The compensation for the faster programming memory cells can also be based on their speed relative to the slower programming memory cells.

Balancing programming speeds of memory cells in a 3D stacked memory

Growing community of inventors

Santa Clara, CA, United States of America

Man Lung Mui