Samsung Electronics Co., Ltd.

Man-Hyoung Ryoo

Si-Hyeung Lee

Gi-Sung Yeo

Hoo-Sung Cho

Sung-Gon Jung

Gyu-Chul Kim

Chang-Min Park

Myeong-Cheol Kim

Moon-Sook Lee

Chang-Jin Kang

Byeong-Ok Cho

Doo-youl Lee

Takahiro Yasue

Sang-Gyun Woo

Hyun-Woo Kim

Jung-hwan Hah

Mitsuhiro Hata

Won-Sun Kim

Jin-young Yoon

Jung-Hwan Hah

Sung-Min Chi

Kyoung-Seon Kim

According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.

Semiconductor device having sufficient process margin and method of forming same

Methods of fabricating a memory unit are provided including forming a plurality of first nanowire structures, each of which includes a first nanowire extending in a first direction parallel to the first substrate and a first electrode layer enclosing the first nanowire, on a first substrate. The first electrode layers are partially removed to form first electrodes beneath the first nanowires. A first insulation layer filling up spaces between structures, each of which includes the first nanowire and the first electrode, is formed on the first substrate. A second electrode layer is formed on the first nanowires and the first insulation layer. A plurality of second nanowires is formed on the second electrode layer, each of which extends in a second direction perpendicular to the first direction. The second electrode layer is partially etched using the second nanowires as an etching mask to form a plurality of second electrodes. Related memory units, methods of fabricating semiconductor devices and semiconductor devices are also provided.

Memory units and related semiconductor devices including nanowires

An integrated circuit semiconductor device including a cell region formed in a first portion of a silicon substrate, the cell region including a first trench formed in the silicon substrate, a first buried insulating layer filled in the first trench, a first insulating pattern formed over the silicon substrate, and a first conductive pattern formed over the first insulating pattern. An overlay key region is formed in a second portion of the silicon substrate and includes a second trench formed in the silicon substrate, a second insulating pattern formed over the silicon substrate and used as an overlay key, and a second conductive pattern formed over the second insulating pattern and formed by correcting overlay and alignment errors using the second insulating pattern. An alignment key region is formed in a third portion of the silicon substrate and includes a third trench formed in the silicon substrate and used as an alignment key, a second buried insulating layer formed in the third trench, and a third conductive pattern formed over the second buried insulating layer and the third trench.

Integrated circuit semiconductor device with overlay key and alignment key and method of fabricating the same

Methods of manufacturing memory units, and methods of manufacturing semiconductor devices

Top coating compositions capable of being used in immersion lithography, and methods of forming photoresist patterns using the same, are provided. The top coating composition includes: a polymer, a base; and a solvent, wherein the polymer may be represented by Formula I: 

Top coating composition for photoresist and method of forming photoresist pattern using same

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Gyeonggi-do, South Korea

Man-Hyoung Ryoo