Bay Microsystems, Inc.

Intel Corporation

Other

Man Dieu Trinh

Simon S Chong

Barry T Lee

Goichiro Ono

Steve C Chen

Anguo Tony Huang

Ryszard Bleszynski

Charles F Gershman

Jun-Wen Tsong

Chi-Hua Chang

Tony J Chiang

Ryzsard Bleszynski

Eric K Yang

Joseph J Senesi

John A Wolf

David A Stelliga

Daniel E Eigenbrode

Srinivas Dabir

Robert S Smedley

Yihui Wu

Richard Smedley

Martin Chang

Ray Chen

Suresh Shelvapille

Anunoy Ghosh

Golchiro Ono

Soochon Radee

Edward Kinzler

Gerard Jankauskas

Systems and methods accessing remote digital data over a wide area network (WAN) are disclosed. In an embodiment, a network device is disclosed. The network device includes a local area network (LAN) switching fabric physical interface configured to communicate according to a LAN switching fabric protocol, a WAN physical interface configured to communicate according to a WAN protocol, and a fabric extension function configured to map LAN switching fabric interfaces to pseudo-ports, map pseudo-ports to WAN interfaces, and transmit LAN fabric datagrams received at the LAN switching fabric physical interface from the WAN physical interface via a mapped pseudo-port and a corresponding WAN interface.

Methods and systems for accessing remote digital data over a wide area network (WAN)

A network processor for processing information elements is described. Each information element is associated with a flow and comprises at least one information element segment. A policy controller stores an information element into at least one information segment storage unit within a memory, and determines whether an information element segment conforms to a predetermined quality of service ('QoS'). A traffic processor selects the information element segment for forwarding based on at least one QoS parameter. A forwarding processor forwards the selected information element segment to an egress port.

Network processor architecture

A hardware-based technique for policing traffic in a network node involves programming a set of algorithm-specific policing primitives that establishes a relationship between condition primitives and action primitives and populating a searchable memory with a set of indexed action primitives. Action primitives are then selected from the searchable memory in response to condition primitives related to a received datagram. Policing actions related to the datagram are performed in response to the action primitive. Because the algorithm-specific policing primitives are programmable, a network node can be adapted to implement a wide variety of policing algorithms. Additionally, multiple different policing algorithms can be implemented in hardware without the need for a different set of combinational logic for each different policing algorithm.

Programmable hardware-based traffic policing

A technique for managing traffic within a network processor integrated circuit (IC) involves establishing multiple queue groups, associating a different hardware counter with each queue group, and then using the hardware counters to support rate shaping and scheduling of all of the queues in the queue groups. For example, 512 queue groups of thirty-two queues each queue group are established for a total of 16,384 (16 k) different queues and a different hardware counter is associated with each queue group for a total of 512 hardware counters. The group-specific hardware counters are used to implement hardware-based rate shaping and scheduling of all 16 k queues in a resource efficient manner that supports high throughput, e.g., on the order of 40 Gbps.

Highly-scalable hardware-based traffic management within a network processor integrated circuit

Systems and methods for queuing and de-queuing packets in a two-dimensional link list data structure. A network processor processes data for transmission for a plurality of Virtual Connections (VCs). The processor creates a two-dimensional link list data structure for each VC. The data field of each data packet is stored in one or more buffer memories. Each buffer memory has an associated buffer descriptor that includes a pointer to the location of the buffer memory, and a pointer pointing to the memory of the next buffer descriptor associated with a buffer memory storing data for the same packet. Each data packet also has an associated packet descriptor including a pointer pointing to the memory location of the first buffer descriptor associated with that packet, and a pointer pointing to the memory location of the packet descriptor associated with the next data packet queued for transmission. A VC descriptor for each VC keeps track of the memory locations of the next packet descriptor and the next buffer descriptor to be de-queued, and the memory locations for storing the next packet descriptors and the next buffer descriptors to be queued.

Two-dimensional queuing/de-queuing methods and systems for implementing the same

A differentiated services device is described. In one embodiment, the differentiated services device includes: a traffic metering unit to indicate whether an information element in a flow conforms to a peak rate and a committed rate; a storage congestion metering unit to determine whether the information element should be accepted or discarded; and a marking unit to mark the information element with one of a plurality of mark values, wherein the marking unit is coupled to the traffic metering unit and the storage congestion metering unit. Also, a method of marking an information element in a flow is described. In one embodiment, the method includes: indicating whether the information element in the flow conforms to a peak rate and a committed rate; determining whether the information element should be accepted or discarded; and marking the information element with one of a plurality of mark values.

Differentiated services for a network processor

An embodiment of this invention pertains to a system and method for balancing memory accesses to a low cost memory unit in order to sustain and guarantee a desired line rate regardless of the incoming traffic pattern. The memory unit may include, for example, a group of dynamic random access memory units. The memory unit is divided into memory channels and each of the memory channels is further divided into memory lines, each of the memory lines includes one or more buffers that correspond to the memory channels. The determination as to which of one or more buffers within a memory line an incoming information element is stored is based on factors such as the number of buffers pending to be read within each of the memory channels, the number of buffers pending to be written within each of the memory channels, and the number of buffers within each of the memory channels that has data written to it and is waiting to be read.

Memory management system and algorithm for network processor architecture

An embodiment of this invention pertains to a network processor that processes incoming information element segments at very high data rates due, in part, to the fact that the processor is deterministic (i.e., the time to complete a process is known) and that it employs a pipelined 'multiple instruction single date' ('MISD') architecture. This MISD architecture is triggered by the arrival of the incoming information element segment. Each process is provided dedicated registers thus eliminating context switches. The pipeline, the instructions fetched, and the incoming information element segment are very long in length. The network processor includes a MISD processor that performs policy control functions such as network traffic policing, buffer allocation and management, protocol modification, timer rollover recovery, an aging mechanism to discard idle flows, and segmentation and reassembly of incoming information elements.

Vertical instruction and data processing in a network processor architecture

The present invention provides techniques for controlling the functionality of a network processor and for facilitating integration of the network processor with a host system. Application programming interfaces (APIs) are provided which can be invoked by the host system for performing device level functions on the network processor. The APIs are provided by a device control module which may execute either on the host system or on the network processor. A host application may invoke an API and the function corresponding to the invoked API is performed by the network processor. Responses or results from the function execution may then be forwarded by the network processor to the host application.

Method and apparatus for issuing commands to a network processor configured to provide a plurality of APIs

The present invention provides application programming interfaces (APIs) which allow a host to control the functioning of a network processor and also perform various network data manipulation functions. The APIs are intended to encapsulate as much as possible the underlying messaging between the host system and the network processor and to hide the low device level command details from the host. The APIs are provided by a program module. A host may invoke an API which is then communicated by the program module to the network processor where functions corresponding to the API are performed. Responses to the APIs may be forwarded back to the host. Asynchronous callback functions, invoked in response to the API calls, may be used to forward responses to the host.

Application programming interfaces and methods enabling a host to interface with a network processor

Systems and methods for storing, or caching, VC descriptors on a single-chip network processor to enhance system performance. The single-chip network processor includes an on-chip cache memory that stores VC descriptors for fast retrieval. When a VC descriptor is to be retrieved, a processing engine sends a VC descriptor identifier to a content-addressable memory (CAM), which stores VC descriptor identifiers in association with addresses in the cache where associated VC descriptors are stored. If the desired VC descriptor is stored in the cache, the CAM returns the associated address to the processing engine and the processing engine retrieves the VC descriptor from the cache memory. If the VC descriptor is not stored in the cache, the CAM returns a miss signal to the processing engine, and the processing engine retrieves the VC descriptor from an off-chip memory. In this manner, VC descriptors associated with high bandwidth VCs are stored to the cache and retrieved much quicker from the cache than from the off-chip memory.

Growing community of inventors

San Jose, CA, United States of America

Man Dieu Trinh