Arm Limited

Man Cheung Joseph Yiu

David Francis McHale

Daren Croxford

Andrew Brookfield Swaine

Paul Kimelman

Ian Field

Gergely Kiss

Nicholas Esca Smith

James Robert Hodgson

Gábor Móricz

Cédric Airaud

A data processing system includes interconnect circuitry providing a plurality of memory transaction paths between one or more transaction masters, including a processor, debugging circuitry and a DMA unit, and one or more transaction slaves including a non-volatile memory, a DRAM memory and an I/O interface. A cache memory is provided between the interconnect circuitry and the non-volatile memory. This cache memory may be a two way set associative cache memory. The cache memory may serve as a read-only cache memory. A cache miss will result in a line fill of a cache line including the target data which was missed. If prefetching is enabled for the cache memory and the transaction was attempting to read a program instruction, then a prefetch operation may be performed in which a further contiguous cache line of data is also fetched into the cache memory upon the cache miss.

Apparatus having cache memory disposed in a memory transaction path between interconnect circuitry and a non-volatile memory, and corresponding method

An interrupt controller is provided for processing interrupt requests in a system having a plurality of data processing units operable to service those interrupt requests, each interrupt request having an associated priority level. The interrupt controller comprises request logic operable to receive an indication of unserviced interrupt requests, to apply predetermined criteria to determine which of said plurality of data processing units are candidate data processing units for servicing at least one of said unserviced interrupt requests, and to issue a request signal to each said candidate data processing unit. Priority encoding logic is operable to determine a highest priority unserviced interrupt request based on the associated priority levels of the unserviced interrupt requests. Further, handshake logic is operable to receive acknowledgement signals associated with said candidate data processing units replying to said request signals issued by the request logic, upon receipt of a first acknowledgement signal, the handshake logic being operable to allocate to the candidate data processing unit associated with that first acknowledgement signal the highest priority unserviced interrupt request as indicated by the priority encoding logic. By this approach, the highest priority unserviced interrupt request will be allocated to the data processing unit whose associated acknowledgement signal is first received by the handshake logic, and hence this increases the speed with which that highest priority interrupt request is serviced.

Handling interrupts in a system having multiple data processing units

An interrupt controller and interrupt controlling method are provided for prioritizing interrupt requests generated by a plurality of interrupt sources. The interrupt controller comprises an interrupt source interface operable to receive interrupt requests generated by a first plurality of interrupt sources, and a daisy chain interface operable to receive a daisy chain interrupt request output by a further interrupt controller based on a second plurality of interrupt requests generated by a second plurality of interrupt sources. The daisy chain interface includes a priority input operable to receive a daisy chain priority signal indicating a priority associated with the daisy chain interrupt request. Prioritization logic is operable to receive the daisy chain priority signal and to apply predetermined prioritisation criteria to determine the highest priority interrupt request selected from the daisy chain interrupt request and the interrupt request generated by the first plurality of interrupt sources. An output interface is operable to output the highest priority interrupt request, the output interface including a priority output operable to provide an output priority signal indicating a priority associated with the highest priority interrupt request.

Interrupt controller and interrupt controlling method for prioritizing interrupt requests generated by a plurality of interrupt sources

A data processing apparatus controls cross-triggering of diagnostic processes on a plurality of processing devices. The data processing apparatus comprises a routing module having a plurality of broadcast channels, one or more of the broadcast channels being operable to indicate the occurrence of a diagnostic event on one or more of the plurality of processing devices. The data processing apparatus also comprises an mapping module associated with a corresponding processing device. The interface module programmably asserts diagnostic event signals from the associated processing device to one or more of the plurality of broadcast channels and programmably retrieves diagnostic events signals from processing devices other than the associated processing device from one or more of the plurality of broadcast channels. The retrieved diagnostic event data is used to facilitate triggering of a diagnostic process on the associated processing device in dependence upon said retrieved diagnostic event data.

Cross-triggering of processing devices

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Maidenhead, United Kingdom

Man Cheung Joseph Yiu