Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Mamoru Seike

Seiichi Moriyama

Jyunichi Suenaga

Mitsuhiro Kasahara

Hiroyuki Kageyama

Kazuyoshi Nishi

Yukihiro Inoue

Tadayuki Masumori

Takashi Ichihara

Akio Niwa

Kazuhito Tanaka

Shuichiro Kojima

Jun Iitsuka

A test pattern generation circuit outputs a test pattern during a clock phase adjustment period. A flip-flop circuit latches the test pattern at the fall of a shift clock and outputs it as a test pattern. A latch miss detection circuit outputs a latch miss detection signal indicating presence/absence of a latch miss generation according to the test pattern and a delay shift clock. A clock phase controller delays the shift clock according to the latch miss detection signal, thereby outputting a delay shift clock.

Plasma display having latch failure detecting function

A display drive device includes a low-voltage circuit section driven by a first power supply potential and a high-voltage circuit section driven by a second power supply potential higher than the first power supply potential. The display drive device further includes a voltage supply circuit for supplying a third power supply potential different from the first and second power supply potentials, a common power supply line for connecting the third power supply potential to each of a plurality of output terminals, an output selection switch circuit for temporarily switching between display data output via the high-voltage circuit section to each output terminal, and the common power supply line, during a predetermined period, and a display data determining circuit for generating a control signal for controlling the output selection switch circuit. Thereby, the common power supply line is temporarily selected and controlled without signal collision when display data is switched.

Display drive device

A first latch circuit temporarily memorizes a display pixel data by one line. A second latch circuit temporarily memorizes the display pixel data as a preceding display pixel data that precedes the display pixel data by one line. The load judging circuit judges a transition state of the display pixel data based on the display pixel data and the preceding display pixel data and predicts a drive load capacity CL based on a result of the judgment. A drivability adjusting circuit adjusts a signal level of the display pixel data based on a result of the prediction of the drive load capacity CL and adjusts drivability of an output.

Display panel drive-control device and display panel drive-control method

A display driver includes: a first memory circuit for storing a line of pixels constituting an image; a second memory circuit for storing pixels of the immediately previous line; an output terminal pair switch circuit which outputs voltages each corresponding to a value of a pixel stored in the first memory circuit to a plurality of output terminals respectively corresponding to the pixels; and an inter-terminal load determination circuit for determining, for every pair of selected columns of pixels constituting the image, whether or not a short circuit is to be established between two of the plurality of output terminals which respectively correspond to the two selected columns based on values of at least three out of four pixels belonging to the two selected columns which are stored in the first and second memory circuits. If the inter-terminal load determination circuit determines that a short circuit is to be established, the output terminal pair switch circuit temporarily establishes a short circuit between the two output terminals before the voltages corresponding to the values of the pixels are output to the two output terminals.

Display driver and display panel module

An N-type diffusion layer fixed at a potential equal to or above 0V is provided in a segregating region between terminals, and a P-type diffusion layer having a potential equal to that of the N-type diffusion layer on an N-type well constitute a drain of a transistor.

Semiconductor circuit device and display data line driver

A driving circuit and a data-line driver is provided which are capable of improving the tolerance to noise between adjacent terminals by using a conventional CMOS process while keeping the chip size small, because a high-density N-diffusion layer () is provided in an isolation region () to minimize a collector current of a parasitic NPN transistor ().

Driving circuit

A driving circuit for the display apparatus having a plurality of output terminals includes a couple of selecting parts for selecting either a potential VDD2 or a potential VDD4 by control signals 221S, 222S, 231S and 2342S and then outputting said selected potentials as V1 and V2, respectively; and a plurality of output parts: say, one of the odd numbered output parts 202 having, in common with other odd numbered output parts, potentials VDD1 and VDD3 and said selected potential V1, and selecting one potential out of them by control signal 241S, 242S and 243S and outputting said selected next potential as a driving signal; one of the even numbered output parts 203 having, in common with other even numbered output parts, said potentials VDD1 and VDD3 and said selected potential V2, and selecting one potential out of them by control signal 251S, 252S, 253S and outputting said selected next potential as a driving signal.

Growing community of inventors

Osaka, Japan

Mamoru Seike