Renesas Electronics Corporation

Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Mamoru Sakugawa

Seiji Ikari

Katsuyoshi Watanabe

Takashi Nasu

Tsutomu Kumagai

Tomohiro Sakurai

Masaru Takahashi

Hiroyuki Kondo

Masamichi Fujito

Jun Setogawa

Shinsuke Yoshimura

Takeshi Hashizume

Kazuhiro Sakashita

Naoto Okumura

There is a need to provide a microcomputer capable of eliminating an external terminal for endian selection. Flash memory includes a user boot area for storing a program executed in user boot mode and corresponding endian information and a user area for storing a program executed in user mode and corresponding endian information. A data transfer circuit reads endian information stored in the user boot area or the user area in accordance with operation mode and supplies the endian information to a CPU before reset release of the CPU. Accordingly, an external terminal for endian selection can be eliminated.

Microcomputer having processor capable of changing endian based on endian information in memory

A data processing device, includes a central processing unit configured to operate in accordance with a program; a register capable of setting a first mode and a second mode; a non-volatile memory; a sequencer configured to control the non-volatile memory; and a first clock circuit for supplying a first clock to the central processing unit and the non-volatile memory, wherein the first mode is a mode in which the central processing unit is operated within a first range of an external supply voltage, wherein the second mode is a mode in which the central processing unit is operated within a second range of the external supply voltage, the second range includes the first range and a relatively low voltage lower than the lower limit voltage of the first range.

Data processing device and data processing system with wide voltage range operation mode

A central processing unit sets which of the following modes a data processing device is to operate in accordance with a user program. The high-speed operation mode allows operation within a first range in which an external supply voltage is relatively high. The wide voltage range operation mode allows operation within a second range in which the external supply voltage includes the first range and a relatively low voltage range, and an upper limit of a frequency of the first clock in the wide voltage range operation mode is lower than an upper limit of a frequency of the first clock in the high-speed operation mode. The frequency of the first clock in the low power consumption operation mode is lower than the frequency of the first clock in the high-speed operation mode and the frequency of the first clock in the wide voltage range operation mode.

A multi-core LSI with improved stability of operation. The multi-core LSI includes a plurality of CPUs coupled to a first shared bus, one or more modules coupled to a second shared bus, a shared bus controller coupled between the first shared bus and the second shared bus for arbitrating access to the module(s) by the CPUs, and a system controller that monitors whether or not a response signal to an access request signal of the CPUs is output from a module to be accessed, wherein the system controller outputs a pseudo response signal to the first shared bus via the shared bus controller to terminate access by the CPU while accessing if the response signal is not output from the module to be accessed after the access request signal is output to the second shared bus from the shared bus controller and before a predetermined time elapses.

Multi-core data processor

To provide a multi-core LSI capable of improving the stability of operation. A multi-core LSI comprises a plurality of CPUs coupled to a first shared bus, one or more modules coupled to a second shared bus, a shared bus controller coupled between the first shared bus and the second shared bus, for arbitrating an access to the module (s) by the CPUs, and a system controller that monitors whether or not a response signal to an access request signal of the CPUs is output from module to be accessed, wherein the system controller outputs a pseudo response signal to the first shared bus via the shared bus controller to terminate the access by the CPU while accessing if the response signal is not output from the module to be accessed after the access request signal is output to the second shared bus from the shared bus controller and before a predetermined time elapses.

To provide a multi-core LSI capable of improving the stability of operation. A multi-core LSI comprises a plurality of CPUs coupled to a first shared bus, one or more modules coupled to a second shared bus, a shared bus controller coupled between the first shared bus and the second shared bus, for arbitrating an access to the module(s) by the CPUs, and a system controller that monitors whether or not a response signal to an access request signal of the CPUs is output from module to be accessed, wherein the system controller outputs a pseudo response signal to the first shared bus via the shared bus controller to terminate the access by the CPU while accessing if the response signal is not output from the module to be accessed after the access request signal is output to the second shared bus from the shared bus controller and before a predetermined time elapses.

A DMA controller comprises an arbitration unit for arbitrating among a plurality of channels so as to select a DMA request from among a plurality of DMA requests accepted by way of the plurality of channels according to priorities assigned to the plurality of channels in advance, and a trace buffer for storing trace data associated with the DMA request selected by the arbitration unit. The DMA controller can also include a write control unit for enabling or disabling writing of the trace data associated with the DMA request selected by the arbitration unit in the trace buffer.

DMA controller having a trace buffer

A microcomputer comprises a CPU, a built-in memory and a memory controller. The memory controller performs access control to the built-in memory in response to a memory access request from the CPU. The microcomputer further comprises a wait count register for storing a waiting period relating to memory access. The memory controller reads the waiting period upon receipt of the memory access request, and then, performs the access control to the built-in memory after a lapse of the waiting period. Low power consumption is achieved by utilizing the access control to the built-in memory without controlling a power source and an oscillator.

Microcomputer and memory access control method

A microprocessor having a built-in DRAM performs following processes: data stored in the buffer,is transferred to the DRAM,through the internal bus,whose data transfer speed is higher than that of the system bus,, the transferring occurring when the number of data input operations by the bus interface unit,reaches a predetermined number &ldquo;p&rdquo;, and an operation result obtained by execution of the CPU,and then stored in the DRAM,is read through the internal bus,and then output to the system bus

Microprocessor having built-in DRAM and internal data transfer paths wider and faster than independent external transfer paths

A semiconductor integrated circuit, which can process n-bit (n is an integer, n&gt;1) instructions or data at a time, has queues for storing instructions or data of m (m&gt;1) times n bits received from an external memory through an instruction bus or a data bus. Therefore, it is possible to achieve an improvement in performance of the semiconductor integrated circuit and further to provide a low-priced semiconductor integrated circuit.

Growing community of inventors

Tokyo, Japan

Mamoru Sakugawa