Hitachi Cable, Inc.

Hitachi, Ltd.

Other

Renesas Electronics Corporation

Renesas Technology Corp.

Hitachi Cable Precision Co., Ltd.

Mamoru Mita

Norio Okabe

Akira Nagai

Ichiro Anjoh

Shuji Eguchi

Makoto Kitano

Asao Nishimura

Gen Murakami

Masahiko Ogino

Chuichi Miyazaki

Hiroyoshi Kokaku

Masanori Segawa

Akira Chinda

Shoji Takagi

Hideki Tanaka

Kunihiro Tsubosaki

Akihiro Yaguchi

Naotaka Tanaka

Ryuji Kohno

Nobutake Tsuyuno

Makoto Morishima

Tetsuo Kumazawa

Nobuaki Miyamoto

Yasuharu Kameyama

Kenji Yamaguchi

Rie Hattori

Tomio Murakami

Toshiak Ishii

Kenji Uchida

Toshiaki Ishii

Hiroki Tanaka

Ryohei Satoh

Takumi Ueno

Koki Hirasawa

Masakazu Ishino

Toyohiko Kumakura

Gen Murakamz

Katsuji Komatsu

Shoji Shinzawa

Katsutoshi Taga

Seigi Aoyama

Takashi Kageyama

Hiroshi Ishikawa

Tetsuo Ishikawa

Akira Matsuura

Sadahiko Mitsugi

Ryozo Yamagishi

Tadashi Kawanobe

Yuichi Ohnuma

Takayuki Yoshiwa

Takayuki Sato

Osamu Yoshioka

An electronic device substrate is provided with a thin-plate core substrate; a metal electrode provided on the core substrate and electrically connected to an electrode of an electronic component to be packaged thereon; and an electrical insulation layer on which is mounted the electronic component, and which is provided to surround the metal electrode.

Method for fabricating an electronic device substrate

Electronic device substrate and its fabrication method, and electronic device and its fabrication method

A lead frame includes a base material, a reflection layer formed on a part of the base material, and a characteristic sustaining layer formed at least on the reflection layer to cover the reflection layer for sustaining a characteristic of the reflection layer by isolating the reflection layer from an outside. The reflection layer includes the characteristic to exhibit a predetermined reflectivity to light with a predetermined wavelength, and the characteristic sustaining layer prevents a decrease in the reflectivity of the reflection layer and transmits light reflected by the reflection layer.

Lead frame, method of making the same and light receiving/emitting device

On both surfaces of an electric insulating material, a surface conductive layerA and a back surface conductive layerB are formed by transcription. Further, a via holepenetrating through the surface conductive layerA and the electric insulating materialis provided. After forming a photosensitive plating resist pattern, the via holeis filled with a copper plating filler, and the surface wiring layerA and the back surface wiring layerB are formed. Thereafter, the photosensitive plating resist patternas well as the surface conductive layerA and the back surface conductive layerB provided under the photosensitive plating resist patternare removed to fabricate a double-sided wiring board

Method for fabricating a multilayer wiring board, multilayer wiring board, and electronic device using the same

A wiring board which can realize a small and thin passive component such as solid condenser, resistor, coil, transistor or so on is provided. A wiring board which forms an electronic component by mounting a passive element, comprising an insulating board provided with an opening having predetermined pattern, a wiring formed with predetermined pattern on said insulating board, and an external terminal filled to said opening, connected with said wiring by said filling, and exposed to a bottom of said insulating board where said wiring is formed.

Wiring board, method for manufacturing wiring board and electronic component using wiring board

A semiconductor device having a superior connection reliability is obtained by providing a buffer body for absorbing the difference of thermal expansion between the mounting substrate and the semiconductor element in a semiconductor package structure, even if an organic material is used for the mounting substrate. A film material is used as the body for buffering the thermal stress generated by the difference in thermal expansion between the mounting substrate and the semiconductor element. The film material has modulus of elasticity of at least 1 MPa in the reflow temperature range (200&#x2013;250&#xb0; C.).

Circuit tape having adhesive film semiconductor device and a method for manufacturing the same

In a semiconductor device having a three-layered buffer layer comprising core layerhaving interconnected foams such as a three-dimensional reticular structure and adhesive layersprovided on both sides of the core layer as a stress buffer layer between semiconductor chipand wiringto lessen a thermal stress generated between the semiconductor device and the package substrate, where a thickness ratio of the core layerto total buffer layer is at least 0.2, the production process can be simplified by using such a buffer layer, thereby improving the mass production capacity and enhancing the package reliability.

Wiring tape for semiconductor device including a buffer layer having interconnected foams

A semiconductor device having a superior connection reliability is obtained by providing a buffer body for absorbing the difference of thermal expansion between the mounting substrate and the semiconductor element in a semiconductor package structure, even if an organic material is used for mounting substrate. A film material is used as the body for buffering the thermal stress generated by the difference in thermal expansion between the mounting substrate and the semiconductor element. The film material has modulus of elasticity of at least 1 MPa in the reflow temperature range (200-250&deg; C.).

Circuit tape having adhesive film, semiconductor device, and a method for manufacturing the same

Semiconductor device, tab tape for semiconductor device, method of manufacturing the tab tape and method of manufacturing the semiconductor device

In a semiconductor device having a three-layered buffer layer comprising core layer having interconnected foams such as a three-dimensional reticular structure and adhesive layers provided on both sides of the core layer as a stress buffer layer between semiconductor chip and wiring to lessen a thermal stress generated between the semiconductor device and the package substrate, where a thickness ratio of core layer to total buffer layer is at least 0.2, the production process can be simplified by using such a buffer layer, thereby improving the mass production capacity and enhancing the package reliability.

Semiconductor device having a porous buffer layer for semiconductor device

A semiconductor device, comprising: a semiconductor chip having on its main plane a plurality of external electrodes each having a joining portion; an insulating substrate having a predetermined pattern of leads thereon and having no device hole for said semiconductor chip, each of said leads being provided with an inner lead having a joining portion which is joined through solder to a corresponding one of the joining portions of said external electrodes of said semiconductor chip to provide a joined portion; and a molding resin for sealing said joined portion including the solder, wherein the joining portion of the external electrode comprises a metal selected from the group consisting of gold and tin, the joining portion of the inner lead comprises a metal selected from the group consisting of gold and tin, provided that, when the metal constituting the joining portion of the external electrode is gold, the metal constituting the joining portion of the inner lead is tin, or vice versa, and the solder comprise gold/tin solder. This constitution contributes to an improved in reliability with respect to temperature cycling in lead-patterning substrates, semiconductor devices, and electronics devices.

Semiconductor device, lead-patterning substrate, and electronics device, and method for fabricating same

A structure of a semiconductor device of a CSP structure is provided. In the semiconductor device, the limitation by the bonding tool is small and the bonding pitch of the semiconductor chip can be reduced to 100 &mgr;m or less, and the chip shrink technique of a technique for lowering the cost can be employed and in connection with this, compatibility among packages can be kept. The semiconductor device comprising a semiconductor chip; a TAB tape being used in a manner being directly laminated onto a circuit formed surface of the semiconductor chip or being laminated through a stress moderating elastomer onto the circuit formed surface of the semiconductor chip, the TAB tape having leads made of a metallic film formed on an insulator tape having flexibility; and an externally connecting member formed in an end of the lead of the TAB tape, wherein the TAB tape has holes in the insulator tape, each of the holes corresponding to a bonding pad formed on a circuit formed surface of the semiconductor chip at a position corresponding to a position of the bonding pad; the lead being formed so as to be bridged across over the hole; the lead formed above the hole being joined to the bonding pad of the semiconductor chip.

Method for bonding a semiconductor chip to a lead-patterning substrate using a gold/tin alloy

A semiconductor device, is provided will semiconductor chips having a plurality of electrodes for external connection, elastomer resin portions formed of an elastomer resin, which are bonded to the semiconductor chip excepting at least some of the plurality of electrodes, a tape layer of resin including tape wiring patterns on the surface thereof, a plurality of solder bumps for bonding the printed wiring pattern to the tape wiring patterns, leads for connecting the plurality of electrodes of the semiconductor chips to the tape wiring patterns, and seal resin for covering the leads and the plurality of electrodes which are connected by the leads. The elastomer resin has a modulus of transverse elasticity not less than 50 MPa and not more than 750 MPa.

Semiconductor device

Growing community of inventors

Hitachi, Japan

Mamoru Mita