Kabushiki Kaisha Toshiba

Tokyo Shibaura Electric Co., Ltd.

Mamoru Kurata

Shin Nakamura

Kouhei Morizuka

Riichi Katoh

Jiro Yoshida

A method of analyzing the operation of a semiconductor device by solving simultaneous equations consisting of electron- and hole-transport equations and Poisson's equation, by means of a computer, thereby to accomplish the modeling of the semiconductor device. The method comprises the steps of: rewriting simultaneous equations to the following equations (a), (b), (c) containing artificial time differential terms dp/dt, dn/dt, d.psi./dt and sensitivity coefficients .lambda.p, .lambda.n, and .lambda..psi.:

Method of analyzing semiconductor device operation, method of analyzing

A heterojunction bipolar transistor comprises a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type formed on the first semiconductor layer, a third semiconductor layer of a second conductivity type formed on the second semiconductor layer, the first, second and third semiconductor layers serving as a collector, a fourth semiconductor layer of the second conductivity type formed on the third semiconductor layer, the fourth semiconductor layer serving as a base, and a fifth semiconductor layer of the first conductivity type formed on the fourth semiconductor layer, the fifth semiconductor layer serving as an emitter, the fourth and fifth semiconductor layers together forming a heterojunction, and the fifth semiconductor layer having a larger band gap than the fourth semiconductor layer, wherein the first, second, third and fourth semiconductor layers are related as follows: ##EQU1## where N.sub.1, N.sub.2, N.sub.3, and N.sub.4 are impurity concentrations of the first, second, third, and fourth semiconductor layers, respectively, e is the unit charge, .epsilon. is the dielectric constant of the collector, V.sub.bi is the built-in potential between the second and third semiconductor layers, and W.sub.3 is the thickness of the third semiconductor layer.

Heterojunction bipolar transistor

A heterostructure bipolar transistor has an emitter layer, a base layer and a collector layer, the emitter layer being formed of a semiconductor material whose energy gap is wider than that of the base layer, so that a heterojunction is formed between the emitter layer and the base layer. One of the emitter layer and the base layer has first and second layers which are sequentially formed, and the first layer constituting the heterojunction has a lower impurity concentration than that of the second layer. When the impurity concentration and the thickness of the first layer are defined as N.sub.1 and W.sub.1, respectively, the following relation is satisfied:

Heterostructure bipolar transistor

A gate turn-off type thyristor comprises a semiconductor body having four sequentially contiguous layers, adjacent two of which are of opposite type conductivity and form a PN junction therebetween, one outer layer constituting a cathode layer of said body being divided into a plurality of mutually independent layer portions; and first and second electrodes packing said semiconductor material body. Between the cathode layer and the electrode is disposed a semiconductor wafer formed with high impurity concentration surface layers for permitting the wafer to ohmically contact with said cathode layer and said electrode, respectively.

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Tokyo, Japan

Mamoru Kurata