Nec Corporation

Renesas Electronics Corporation

Niigata Seimitsu Co., Ltd.

Elpida Memory, Inc.

Koa Glass Co., Ltd

Mamoru Kitamura

Keisuke Fukuda

Motoaki Suzuki

Makoto Nakamura

Kenichi Tanaka

Yoshinao Kobayashi

Shinobu Kanamaru

An LED drive method drives an LED by a drive current. The LED drive method uses a voltage conversion unit, which includes a coil and a first switch, and converts an external voltage into a first voltage, which is a DC voltage, by controlling the first switch to be on in an on-pulse period of a first drive signal. A constant current drive unit is provided with the first voltage and generates a drive current based on a second drive signal.

LED drive method and LED drive device

An LED lighting deviceaccording to this embodiment includes a lighting circuit that supplies a current to an LED, and a dimmerthat generates a PWM signal for controlling the supply of the current to the LED from the lighting circuit, in which the dimmerfeedback-controls the PWM signal that controls the supply of the current to the LED by comparing the output current to be output to the LED with a target current and feedforward-controls the PWM signal according to a fluctuation of an input voltage from a commercial power supply

LED lighting device and LED illuminating device

A semiconductor device configured to perform an A/D conversion of a wide range of signals is provided. A semiconductor device includes: an input voltage detection unit configured to detect an analog input voltage; a reference voltage setting unit configured to set a reference voltage based on the detected input voltage; an amplifier configured to amplify a difference between the input voltage and the reference voltage; an ADC configured to perform an A/D conversion of an amplified signal; and an arithmetic processing unit configured to calculate a digital voltage corresponding to the input voltage based on a result of the A/D conversion and the reference voltage.

Semiconductor device, power supply device and control method for semiconductor device

A voltage conversion unit including a coil and a first switch converts an AC voltage into a first voltage, which is a DC voltage, by controlling the first switch to be on in an on-pulse period of a first drive signal. A constant current drive unit is supplied with the first voltage and generates a drive current Id having a current value according to light control information. An LED control unit compares brightness based on the light control information and reference brightness, generates a first drive signal based on an error between the first voltage and a target voltage representing a target of the first voltage, when the brightness is higher than the reference brightness, and generates the first drive signal having a predetermined fixed on-pulse period when the brightness is lower than the reference brightness.

An antimicrobial glass is provided which can release a predetermined amount of silver ion rapidly for a long period of time and can provide a predetermined antimicrobial treatment repeatedly to a matter to be antibacterialized during or after washing and which is excellent in discoloration prevention effect and discriminativity, and a method for producing the same is also provided. A tabular antimicrobial glass capable of exerting an antimicrobial effect by releasing silver ions, wherein the maximum diameter (t) is adjusted within the range of 3 to 30 mm and which contains an inorganic coloring agent as a compounded component, wherein the addition amount of the inorganic coloring agent is adjusted to a value within the range of 0.001 to 0.5% by weight to the total amount.

Antimicrobial glass and method of producing antimicrobial glass

A dynamic random access memory (DRAM) includes a data signal input circuit configured to input a data signal in response to a data control signal, and a data strobe signal input circuit configured to input a data strobe signal in response to a data strobe control signal. A control circuit separately generates the data control signal and the data strobe control signal. A data latch circuit latches the data signal from the data signal input circuit in response to the data strobe signal from the data strobe signal input circuit. A memory cell array has a plurality of memory cells arranged in a matrix. The latched data signal is stored in a selected one of the plurality of memory cells through the data buffer, an amplifier circuit configured to amplify a data signal read out from the selected memory cell; and an output circuit configured to output the amplified data signal.

Semiconductor memory device with no latch error

A comparator () for compensating the pulse width of the drive control signal of a power amplifier () by using a sense signal of an offset voltage generated between the nodes (H, I) of the power amplifier () is provided to enlarge the time width from the OFF operation of a pair of switching elements (QQ) to the ON operation of a pair of switching elements (QQ), thereby preventing the inconvenience that the switching elements (QQ) simultaneously turn on and suppressing a through-current. The pulse width for turning on the switching elements (QQ) is so corrected as to be wider or narrower than the pulse width for turning on the switching elements (QQ), thereby adjusting the intensity of an impressing voltage and canceling the offset voltage.

Audio reproducing apparatus and method

A digital &#x394;&#x3a3; modulated signal produced by a quantizer () in a &#x394;&#x3a3; modulation processing unit () is put in to a feedback loop before inputted to a power switch () and converted into an analog signal by a D/A converter (). This analog signal is fed back to the input stage (a differentiator ()) of the &#x394;&#x3a3; processing unit () to prevent the switching distortion of the power switch () itself from being introduced into the feedback loop thereby to suppress the influence of the switching distortion.

Audio reproducing device and method, audio amplifier, and integrated circuit for audio amplifier

A transformer, which converts input current into voltage output, is arranged between a power switch, which amplifies and outputs audio signals based on the power source voltage VDD supplied to MOS transistors Qto Q, and a speaker. Through appropriately determining the turns ratio (Ns/Np), without causing the power source voltage VDD of the power switchto be large, large voltage Vs is made to occur at both ends of the speakerfrom such small power source voltage VDD. Through this, large output power can be obtained.

Audio amplifier

A semiconductor memory device includes an internal clock signal generating section for generating an internal clock signal from an external clock signal. A latch section includes an address latching circuit for latching an inputted address, a command latching circuit for latching an inputted command and a write data latching circuit for latching an inputted write data. A state setting section controls the address latching circuit, the command latching circuit and the write data latching circuit based on an address key latched by the address latching circuit and a mode setting command latched by the command latching circuit such that a time difference is selectively extended between a first timing of the internal clock signal and a second timing for each of the address, the command and the write data to be changed.

Semiconductor memory device having extended margin in latching input

A power conserving circuit configuration is presented which reduces the power supplied to the input/output pins in the initial input circuit in a synchronous semiconductor device. The circuit reduces the power to the input/output pins in the initial input circuit during the standby mode and/or readout mode, and restores the power to the initial input circuit, when an input signal is entered in an external disabling pin which generates an output disabling signal, which makes the output signal from the input/output pin to be nullified and causes the power to be restored in the synchronous semiconductor device.

Power reducing circuit for synchronous semiconductor device

A synchronized semiconductor memory device comprising a memory cell array, an address input circuit, an address set circuit, a command input circuit, a data reading/writing control circuit, a data output circuit, a data input circuit, a clock input circuit, an internal clock generating circuit, an internal clock timing control circuit. The clock input circuit comprises first and second clock input circuits, and the internal clock generating circuit comprises a first internal clock generating circuit receiving a clock information from the first clock input circuit, for generating a fist reference internal clock signal controlling the address input circuit, the address set circuit, the command input circuit, the data reading/writing control circuit, the data output circuit and the data input circuit, and a second internal clock generating circuit receiving a clock information from the second clock input circuit, for generating a second reference internal clock signal controlling only the data output circuit.

Synchronized semiconductor memory

A synchronized semiconductor memory device comprises a memory cell array, an address input circuit, an address set circuit, a command input circuit, a data reading/writing control circuit, a data output circuit, a data input circuit, a clock input circuit, an internal clock generating circuit, and an internal clock timing control circuit. The internal clock timing control circuit includes a delay circuit to receive a reference internal clock generated in the internal clock generating circuit, a plurality of level signals set in accordance with a given mode register set cycle, and a plurality of row address enable signals, and for generating at least an internal clock signal for timing-controlling the data reading/writing circuit. The internal clock timing control circuit also includes a logic circuit to receive the reference internal clock generated in the internal clock generating circuit and the plurality of row address enable signals, and for generating another internal clock signal for timing-controlling the data input circuit.

A semiconductor device according to the invention includes a first layer including first and second device regions, in which semiconductor devices are formed; and a second layer including a signal line region, a first power supply region, which is one selected between power source and ground and a second power supply region which is the remaining of the power source and ground, the second power supply region being horizontally positioned between the signal line and first power supply regions. The first device region is positioned under both said first and second power supply regions. The second device region is positioned under the signal line region and the second power supply region.

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Tokyo, Japan

Mamoru Kitamura