Mitsubishi Denki Kabushiki Kaisha

Mamoru Katoh

Kaoru Abe

Takashi Tanabe

Toshihisa Kamemaru

Toyohito Hatashita

Tsugihiko Ohno

Masakazu Soga

Hiromu Okamoto

Norihisa Kaneda

A fault recovery process of a computer is provided for removing a fault from the system as soon as possible, minimizing the secondary fault and improving the availability of the system. In a reliable computer, which includes a system bus, a main memory connected to the system bus, and at least one processing board connected to the system bus, at least one processing board executes the same instructions by n (n&gt;=3) processing units having cache memories respectively. When one of the processing units of the processing board becomes faulty, the other processing units continue executing the processes, which are being executed by the faulty processing board, and then, the processes to be registered in the faulty processing board, are succeeded by other processing boards.

Processing board, a computer, and a fault recovery method for the

This invention provides a majority circuit, connecting a plurality of processing units. The majority circuit can detect a single error or multiple errors, and sets the majority output signal to an ineffective level when multiple errors are detected. The majority circuit includes comparators, each comparing two outputs of three processing units, and the error detector recognizes the error status and outputs the single error signal and the multiple error signal accordingly. The majority circuit also includes a selector, which selects the output of a normal processing unit, when the normal processing unit can be specified based on the comparison result. The selector changes the output to a predetermined level, when the normal processing unit cannot be specified.

Majority circuit, a controller and a majority LSI

Growing community of inventors

Kanagawa, Japan

Mamoru Katoh