Hitachi, Ltd.

Mamoru Hinai

Kenichi Wada

Chikahiko Izumi

Kazuo Hibi

In a data processing system having a buffer storage and operated in a virtual storage system, storage keys including reference bits are retained in a storage key memory one for each predetermined unit of real storage, and reference bits are retained in a reference bit memory one for each predetermined unit of the real storage. Whenever the real storage is referred, the corresponding reference bit of the storage key memory is set, and whenever the buffer storage is referred, the corresponding reference bit of the reference bit memory is set. The reference bit of the storage key memory and the reference bit of the reference bit memory are ORed to produce a true reference bit.

Data processing system providing dual storage of reference bits

The alignment of data as required in an L-stage is carried out with a first aligner which is controlled by a wired logic for exclusive use, while the alignment of data as required in an E-stage is carried out with a second aligner which is controlled by a microinstruction. Regarding those among macroinstructions which need to fetch storage operands in only the L-stages, the alignment of the storage operand is carried out by means of the first aligner. On the other hand, in the execution of macroinstructions which need to fetch storage operands in both the L-stages and the E-stages, the storage operands fetched in the L- and E-stages are respectively aligned by means of the first and second aligners.

Microinstruction controlled data processing system including

A multiple virtual storage control system for a data processing system for handling a plurality of virtual spaces is disclosed. Virtual addresses indicative of addresses in the virtual spaces are translated to real addresses by a translation table. When a new virtual space is established by setting a first address or segment table origin address (STO address) of the translation table, a virtual space number is assigned to the established virtual space by an STO address stack, which comprises a definite number of registers. The number of virtual space numbers assigned is larger than the number of registers. The virtual addresses and the corresponding real addresses are stored in a high-speed address translator so that the virtual addresses are translated to the real addresses at a high speed. When an overflow of the virtual space number assigned in the STO address stack takes place, the plurality of virtual spaces registered in the high-speed address translator are simultaneously purged.

Multiple virtual storage control system

Disclosed is a data processing system comprising means for storing a plurality of macroinstructions and data, means for determining a starting address of data participating in practice of a macroinstruction read out from the storing means and the entire length of said data in response to said read-out macroinstruction and reading out said data from said storing means based on the thus determined address and entire length, means for shifting the read-out data by a quantity determined by said macroinstruction and means for masking a part, determined by said macroinstruction, of said shifted data, wherein practice of macroinstructions is controlled by a microinstruction sequence, an align field is disposed for these microinstructions to control said read-out means, shifting means and masking means, said shifting means is arranged so that said shifting quantity is determined in response to said starting address and said align field, and means for putting out mask pattern signals indicating the position of data to be masked in response to said entire length of data, said starting address and said align field is disposed in said masking means.

Growing community of inventors

Hadano, Japan

Mamoru Hinai