Nec Corporation

Yoshino Kogyosho Co., Ltd.

Snow Brand Milk Products Co., Ltd.

Snow Brand Milk Products, Ltd.

Mamoru Fujita

Yoshito Shibauchi

Tadashi Hanada

Kohichi Hatanaka

Tatsuo Tanaka

Katsuyuki Mogi

Tadahiko Sugibayashi

Satoshi Isa

Isao Naritake

Hironobu Terajima

A semiconductor memory device is provided that can shorten the precharge time and accelerate the access time of the memory without increasing the chip size. The sense amplifier selection circuit outputs a precharge control signal PDLD that carries out a specified precharge of bit lines BLT to BLTN and bit lines BLN to BLNn connected to sense amplifiers SA to SAn. A voltage transformer circuit transforms the voltage value at H level of the input precharge control signal PDLB to a voltage VDV having a value higher than the value &ldquo;Vcc&plus;Ct &rdquo;, which is the voltage power source Vcc added to the threshold value voltage Vt of the MOS transistors NM of the precharge drive circuits to , and outputting the result as the precharge drive voltage PDLD. The precharge drive circuits to are formed in the cross region, and formed by n-channel type MOS transistor NM and n-channel type MOS transistor NM

Semiconductor memory device

A semiconductor memory device in which a memory cell array is divided into a plurality of operation blocks and one regular word line is activated simultaneously in each of two or more operation block. In the semiconductor memory device, when a defective regular word line is set for replacement with a spare word line, data is recorded in fuse ROM (read only memory) in the semiconductor memory device such that a regular word line to be replaced and a replacing spare word line are located in the same operation block or not located each in combined operation blocks which are activated simultaneously. This can prevent the simultaneous activation of a regular word line and a spare word line in the same operation block and malfunction of the semiconductor memory device.

Method and apparatus for setting redundancy data for semiconductor memory device

A semiconductor memory device having redundant memory selection circuit XRDN which outputs a redundant replacement selection signal for each bank. In a refreshing operation, each redundant decoder XRED only compares an address indicated by row address signal XADD with an address of a defective memory cell stored, without referring to a bank selection signal included in row address signal XADD. Redundant memory cell selection circuit XRDN outputs redundant replacement selection signals XRDNS(A), (B) for respective banks A, B, for indicating a bank in which the replacement is to be performed with a redundant memory cell.

Semiconductor memory device with redundancy function

In a semiconductor memory device including a plurality of sense amplifiers arranged in rows, columns, a plurality of local data input/output line pairs, each pair being connected to one row of the sense amplifiers, a global data input/output line pair, a plurality of switches each connected between one of the local data input/output line pairs and the global data input/output line pair, and a differential amplifier connected to the global data input/output line pair, at least one pull-up circuit is connected to the global data input/output line pair. At least one of the switches is connected to the global data input/output line pair between the pull-up circuit and the differential amplifier.

Semiconductor memory device capable of improving read operation speed

A semiconductor memory includes a plurality of memory cell arrays each composed of a plurality of memory cells, each of the memory cell arrays including a plurality of main word lines, each of which is composed of a pair of sub-word lines each connected to a plurality of memory cells, means for driving the main word lines, power supply voltage supply line driving means connected to the sub-line lines. When a redundant word line used in place of a specific sub-word line including a defective sense amplifier is activated, the number of the sub-word lines activated when a data input/output is conducted is different from the number of sub-word lines activated in a refreshing operation. When the data input/output is conducted, a replacement of a sub-word line is executed on the basis of the result of a comparison between an externally supplied row address and an internally stored row address. When the refreshing operation is conducted, the replacement of the sub-word line is executed on the basis of an output of an internal refresh address counter and simultaneously with an ordinary refreshing operation.

Semiconductor memory

A semiconductor memory of the present invention includes a plurality of memory cell regions each being constituted by a particular memory cell and a plurality of word lines for selecting the memory cells. A word line driver circuit activates one word line to which a memory cell designated by the address signal is connected. A bit line connected to the memory cell selected by the activated word line reads data out of the memory cell. A sense amplifier amplifies a potential difference between two adjoining bit lines forming a bit line pair. A sense amplifier precharge circuit charges a power supply line and a ground line, which feed a voltage to the sense amplifier, to a preselected voltage. A driver circuit feeds to the gates of a first and a second n-channel MOS transistors in the sense amplifier precharge circuit a control signal of a preselected high level voltage from a third n-channel MOS transistor. The first and second n-channel MOS transistors feed a precharge current output from a precharge power supply to the power supply line and ground line, respectively. The sense amplifier precharge circuit may be replaced with or combined with an I/O line precharge circuit for precharging I/O lines.

Semiconductor memory device having means for outputting redundancy

The present invention provides a synchronous memory device having at least a multi-bit pre-fetch address generator circuit, and at least an access path which includes at least a command decoder having an output terminal connected to at least a follower circuit element which receives a command signal from the at least a command decoder, wherein the at least a multi-bit pre-fetch address generator circuit is connected to the at least a follower circuit element in parallel to the at least a command decoder, so that the at least a multi-bit pre-fetch address generator circuit is excluded from a transmission path of the command signal, whereby the at least a multi-bit pre-fetch address generator circuit generates a plurality of internal address signals independently from transmission of the command signal from the at least a command decoder to the at least a follower circuit element.

Synchronous semiconductor memory device having burst access mode and

A semiconductor memory device is provided that includes a plurality of normal memory cells, a device for activating the memory cells in response to an externally applied address and a plurality of redundant memory cells. A memory and comparison device may include a device for storing an address of a failed memory cell existing within a plurality of normal memory cells and a device for comparing the externally applied address with the failed memory cell address. A redundant memory cell selection device may select any one of a plurality of redundant memory cells in response to an output signal output from the memory and comparison device. A redundant memory cell activating device may activate the redundant memory cell, responsive to an output of the memory and comparison device.

High efficiency redundancy scheme for semiconductor memory device

A semiconductor memory device comprising a plurality of memory cell arrays including a redundant memory cell for each. Connection between each memory cell array and data input-output terminals can be switched easily by a signal input from the outside in response to a plurality of input-output data widths. Each redundant memory cell compares each bit of an external address input externally with each bit of an internal address of a memory cell having been stored. According to a detection signal from a redundancy judging circuit to detect agreement between both addresses, the memory cell having that address is replaced. This replacement can be carried out not only within the memory cell array having the redundant memory cell but also between different memory cell arrays.

External control signals are input to a semiconductor memory device via a synchronizing semiconductor circuit. An internal clock (ICLK) in the synchronizing semiconductor circuit is produced as a phase shifted version of an external clock (S11) which is input to the memory device. First latch circuits (321-324) latch external control signals in response to the external clock (S11). Decoder circuits (331.sub.0 -331.sub.n) produce internal control signals (S31.sub.0 -S331.sub.n) based upon the latched signals (S21-S24) output from the first latch circuits (321-324). Second latch circuits (341.sub.0 -341.sub.n) latch the internal control signals (S31.sub.0 14 S31.sub.n) in response to the internal clock signal (ICLK).

Semiconductor memory having signal input circuit of synchronous type

A semiconductor memory device has an input circuit for inputting reference clocks, an input buffer circuit for latching external input signals in synchronization with the reference clocks, and an output buffer circuit for outputting a stored data to an outside in synchronization with the reference clocks. The input buffer circuit and the output buffer circuit are caused to operate at respectively different edges of the reference clocks for processing one and the same stored data. The device may include an internal read-out circuit system which reads-out the stored data in accordance with the external input signal and which is caused to operate solely based on an edge at which the input buffer circuit operates. Between the internal read-out system and the output buffer circuit, there is provided a buffer circuit which temporarily stores the stored data read-out by the internal read-out circuit system until the stored data is outputted by the output buffer. The arrangement enables the provision of a high burst mode memory device in which almost no additional gate delay and no increase in its area.

High speed semiconductor memory with burst mode

Method and apparatus for forming seal portion of laminated aluminum tub

To obtain high access speed regardless of a structure and operating characteristics of an external central processing unit (CPU), a synchronous dynamic random access memory (DRAM) system includes first and second DRAM cell arrays, and a first address generator for outputting a first address and a second address respectively to the first and second DRAM cell arrays simultaneously in a first mode. In a second mode, the first address generator outputs the first address and the second address respectively to the first and second DRAM cell arrays sequentially.

Growing community of inventors

Tokyo, Japan

Mamoru Fujita