Ntt Electronics Corporation

Mami Mikami

Yuki Yoshida

Masahiro Tachibana

A data transfer circuit according to the invention includes a memory configured to write data in accordance with a write pointer in synchronization with a first clock, and read out the data in accordance with a readout pointer in synchronization with a second clock, a clock generation circuit configured to generate the second clock by multiplying a reference clock by a rational number N, a frequency error estimation circuit configured to estimate a frequency error between the first clock and the second clock based on a change amount of a pointer difference between the write pointer and the readout pointer, and an adjustment circuit configured to output, as an adjustment multiple ΔN, a value obtained by dividing the estimated frequency error by a frequency of the reference clock. The clock generation circuit generates the second clock by multiplying the reference clock by a rational number (N+ΔN).

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Yokohama, Japan

Mami Mikami