Kabushiki Kaisha Toshiba

Mami Kawabata

Masahiro Yoshihara

Eiichi Makino

Naoaki Kanagawa

Shintaro Hayashi

Manabu Satoh

A semiconductor memory device adopting a bit line twist system in which at least a part of bit lines are twisted, includes memory cell arrays each having a plurality of memory cells to store data, redundancy cell arrays each having a plurality of redundancy cells to replace a defective cell in the memory cell array, and a control circuit which performs control to invert a direction of the data. The device further includes an inversion circuit which inverts the direction of the data, in accordance with the control by the control circuit.

Semiconductor memory device of bit line twist system

A semiconductor device comprises a first transistor and a potential generator circuit. The first transistor has a first conduction type first semiconductor region and a second conduction type second semiconductor region formed in the first semiconductor region. The first and second semiconductor regions are supplied with first and second prescribed potentials, respectively. The potential generator circuit generates the first prescribed potential. The potential generator circuit has a first power supply terminal supplied with a first power supply potential, a second power supply terminal supplied with a second power supply potential set to a higher potential than the first power supply potential, and an output terminal outputting the first prescribed potential. The potential generator circuit outputs the second power supply potential when the second power supply potential is higher than a predetermined potential, and the first power supply potential when the second power supply potential is lower than the predetermined potential.

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Yokohama, Japan

Mami Kawabata