Kioxia Corporation

Toshiba Memory Corporation

Mami Kakoi

Akio Sugahara

Masahiro Yoshihara

Naofumi Abiko

Toshifumi Watanabe

Akihiro Imamoto

Kohei Masuda

Yasuhiro Hirashima

Shinya Okuno

A semiconductor memory device according to an embodiment includes a plurality of planes each including a plurality of blocks each including a memory cell, an input/output circuit configured to receive a command set from an external controller, and a sequencer configured to execute an operation in response to the command set. Upon receiving a first command set that instructs execution of a first operation, the sequencer executes the first operation. Upon receiving a second command set that instructs execution of a second operation during execution of the first operation, the sequencer executes the second operation in parallel with the first operation. Upon receiving a third command set that instructs execution of a third operation during execution of the first operation, the sequencer suspends the first operation, executes the third operation, and resumes the first operation upon completion of the third operation.

Semiconductor memory device

A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.

A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation, and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.

A semiconductor memory device includes a plurality of memory chips that are stacked above one another and connected to each other through a through via, an interface chip that is connected to the plurality of memory chips, and a plurality of first terminals for connection with an external device. The interface chip includes a plurality of second terminals that are connected to the plurality of first terminals, and is capable of receiving a signal that is supplied from the external device through the first and second terminals, and stores configuration information according to which a set number of the second terminals are designated for receiving control signals for the plurality of memory chips.

Growing community of inventors

Yokohama Kanagawa, Japan

Mami Kakoi