Synopsys, Inc.

Malitha Kulatunga

Rajarshi Mukherjee

Kaushik De

David L Allen

Bhaskar Pal

Sanjay Gulati

Sachin Bansal

Gaurav Pratap

Nishant Patel

State table complexity reduction in a hierarchical verification flow is provided by identifying peripheral supplies and non-peripheral supplies in a hierarchical group in a hierarchical logical block model of a circuit based on whether logic blocks associated with the power supplies provide outputs to or receive inputs from circuity external to the hierarchical group; merging associated power state tables for the peripheral supplies and the non-peripheral supplies in the hierarchical group to create a merged power state table for the hierarchical group; removing, by a processing device, any power states associated with the non-peripheral supplies from the merged power state table to create a reduced power state table; and modeling a reduced logical block based on the reduced power state table.

State table complexity reduction in a hierarchical verification flow

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Colombo, Sri Lanka

Malitha Kulatunga