International Business Machines Corporation

Malede Wondmagegne Berhanu

Clarence Rosser Ogilvie

David W Milton

Jack Robert Smith

Mark William Kuemerle

Christopher Douglas Hanudel

Vikram Iyengar

Douglas C Pricer

Konda R Baalaji

A method and system is provided for automatically generating valid at speed structural test (ASST) test groups. The method includes loading a netlist for an integrated circuit into a processor. The method further includes determining a plurality of clock domain crossings between a plurality of clock domains within the integrated circuit. The method further includes generating a first test group. The method further includes adding a first clock domain of the plurality of clock domains to the first test group. The method further includes adding a second clock domain of the plurality of clock domains to the first test group when the second clock domain does not have a clock domain crossing into the first clock domain.

Automatic generation of valid at-speed structural test (ASST) test groups

A structure for performing cross-chip communication with mesochronous clocks. The structure includes: a data delay line; a remote clock delay line; a structure that captures at least one value of a state of a delayed remote clock signal on the remote clock delay line; and a control that influences a delay associated with the data delay line and the remote clock delay line.

Method, circuit, and design structure for capturing data across a pseudo-synchronous interface

A method for source synchronous communication. The method includes dynamically adjusting a delay that is applied to a data signal and a remote clock signal until a delayed remote clock signal is synchronized with a local clock signal, and capturing data from a delayed data signal associated with the delay in a local domain.

In one general embodiment, a design structure is provided including a first delay line having at least one buffer, the first delay line being for shifting a clock, a second delay line having at least one buffer, the second delay line being for shifting data, and a logic block adapted to identify a predetermined section of a data window. Additionally, the logic block monitors a clock signal along predetermined portions of the delay line to identify the predetermined section of the data window. Once the predetermined section of the data window is identified the logic block forwards the data associated with the predetermined section to an output pin, with the proviso that no memory element is present, and with the proviso that no feedback line is present.

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Colchester, VT, United States of America

Malede Wondmagegne Berhanu